dsPIC33AK256MPS305 CACHE registers

The 16 registers of CACHE (CACHE), from 0x1E60, with their reset value and every field. The dsPIC33AK256MPS305 has 1671 registers in 88 peripherals, one page each.

CACHE CACHE

CHECONCache Control

Address
0x1E60
Reset
0x00008400
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
ISBBUF16ISB Buffer Selection
ON15Cache ON
CHEINV11Manual Invalidate Control
CHECOH10Cache Coherency Control
CP7Cache Pause
FLTINJ0Fault Inject Control

CHESTATCache Status

Address
0x1E64
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ISBPE3ISB Parity Error Status
TPE2TAG Parity Error Status
ISBE1Read Error Status
PARE0Cache Parity Error Status

CHEFLTINJFault Injector

Address
0x1E68
Reset
0x000000FF
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FLTPTR7:0Fault Injection Pointer

CHEDAT0Cache Ram Data/Compare 0

Address
0x1E6C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
WORD31:032 bit Instruction Word in cache

CHEDAT1Cache Ram Data/Compare 1

Address
0x1E70
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
WORD31:032 bit Instruction Word in cache

CHEDAT2Cache Ram Data/Compare 2

Address
0x1E74
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
WORD31:032 bit Instruction Word in cache

CHEDAT3Cache Ram Data/Compare 3

Address
0x1E78
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
WORD31:032 bit Instruction Word in cache

CHECMDCache Ram Address/Control

Address
0x1E7C
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
WIP27:24Direct write of parity bits (requires EWP=1), read back of written data
CMPP22Compare Addressed cache RAM line parity to WIP (Register returns comparison result in Read mode)
EWP21Enable WIP bits direct write to cache RAM parity bits
EWD20Enable Data write to cache RAM
CMPD19Compare Cache RAM contents to data registers
RD18Read trigger for 4 register values from cache RAM to CHEDAT register, and 4 cache parity bits to RIP bits
RVAL13Value read FROM TAG in addressed cache
WVAL12Value written TO TAG in addressed cache
CMPV11Compare WVAL to TAG valid bit in current cache line
WV10Write WVAL to TAG valid bit in cache line
ADDR6:0Address of 128bit 4 word cache line
RIP31:28Read value of parity bits

TAGDATTAG Data

Address
0x1E80
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADDR23:11Tag data

TAGCMDTag Control

Address
0x1E84
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
RTP026Read value of TAG parity bit 0
WTP025Direct write of TAG parity bit 0 (requires EWP=1), read back written data
CMPP22Compare addressed cache TAG parity to WTP0 bit (Register returns comparison result in Read mode)
EWP21Enable TAG parity bit to direct write to TAG ram parity bits
EWD20Enable 24 bit address in data register to TAG ram write
CMPA19Compare addressed cache TAG to address register content
RD18Trigger Read/Write to address cache RAM
ADDR6:0Address of 128bit 4 word cache line

ISBDAT0ISB Stream Buffer Data 0

Address
0x1E88
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
WORD31:032 bit Instruction Word in ISB

ISBDAT1ISB Stream Buffer Data 1

Address
0x1E8C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
WORD31:032 bit Instruction Word in ISB

ISBDAT2ISB Stream Buffer Data 2

Address
0x1E90
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
WORD31:032 bit Instruction Word in ISB

ISBDAT3ISB Stream Buffer Data 3

Address
0x1E94
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
WORD31:032 bit Instruction Word in ISB

ISBCMD0ISB Control 0

Address
0x1E98
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
WIP27:24Write parity data, requires EWP = 1
CMPP22Compare contents of parity bit
EWP21Enable manual write of parity bits
EWD20Enable manual write of data bits
CMPD19Compare the contents of addressed ISB register to contents of data registers. Used to compareslice data so only valid if ISBREG[2:0] set to 101 = isb_slice_data
RD18: Read 4 32bit register valued to address cache RAM, parity bits into ISBCMD.RIP
LINE10:8ISB buffer line address, 0-7
ISBREG7:5ISB register access select
RIP31:28Valid when reading ISB data register

ISBCMD1_7ISB Control 1

Address
0x1E9C
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
FieldBitsWhat it does
WIP27:24Write parity data, requires EWP = 1
CMPP22Compare contents of parity bit
EWP21Enable manual write of parity bits
EWD20Enable manual write of data bits
CMPD19Compare the contents of addressed ISB register to contents of data registers. Used to compareslice data so only valid if ISBREG[2:0] set to 101 = isb_slice_data
RD18: Read 4 32bit register valued to address cache RAM, parity bits into ISBCMD.RIP
LINE10:8ISB buffer line address, 0-7
ISBREG7:5ISB register access select
SLICE2:0ISB buffer slice address, 0-7
RIP31:28Valid when reading ISB data register