BETASSP1BUF
- Address
0x78C- Reset
x (not fixed at power-on)- Access
- read/write
- 7SSPBUF7
- 6SSPBUF6
- 5SSPBUF5
- 4SSPBUF4
- 3SSPBUF3
- 2SSPBUF2
- 1SSPBUF1
- 0SSPBUF0
1 field
| Field | Bits | What it does |
|---|---|---|
| SSPBUF | 7:0 |
PIC16F17554 MSSP registers
The 20 registers of MSSP (Master synchronous serial port (SPI, I²C)), from 0x78C, with their reset value and every field. The PIC16F17554 has 456 registers in 43 peripherals, one page each.
MSSP Master synchronous serial port (SPI, I²C)
SSP1ADD
- Address
0x78D- Reset
0x00- Access
- read/write
- 7SSPADD7
- 6SSPADD6
- 5SSPADD5
- 4SSPADD4
- 3SSPADD3
- 2SSPADD2
- 1SSPADD1
- 0SSPADD0
1 field
| Field | Bits | What it does |
|---|---|---|
| SSPADD | 7:0 |
SSP1MSK
- Address
0x78E- Reset
0xFF- Access
- read/write
- 7SSPMSK7
- 6SSPMSK6
- 5SSPMSK5
- 4SSPMSK4
- 3SSPMSK3
- 2SSPMSK2
- 1SSPMSK1
- 0SSPMSK0
1 field
| Field | Bits | What it does |
|---|---|---|
| SSPMSK | 7:0 |
SSP1STATMSSP1 STATUS REGISTER
- Address
0x78F- Reset
0x00- Access
- read/write
- 7SMP
- 6CKE
- 5D_nA
- 4P
- 3S
- 2R_nW
- 1UA
- 0BF
8 fields
| Field | Bits | What it does |
|---|---|---|
| SMP | 7 | SPI Data Input Sample Phase bit |
| CKE | 6 | SPI Clock Edge Select bit |
| D_nA | 5 | Data/Address bit |
| P | 4 | Stop bit |
| S | 3 | Start bit |
| R_nW | 2 | Read/Write Information bit |
| UA | 1 | Update Address bit |
| BF | 0 | Buffer Full Status bit (Receive mode only) |
SSP1CON1
- Address
0x790- Reset
0x00- Access
- read/write
- 7WCOL
- 6SSPOV
- 5SSPEN
- 4CKP
- 3SSPM3
- 2SSPM2
- 1SSPM1
- 0SSPM0
5 fields
| Field | Bits | What it does |
|---|---|---|
| WCOL | 7 | Write Collision Detect bit (Transmit mode only) |
| SSPOV | 6 | Receive Overflow Indicator bit |
| SSPEN | 5 | Synchronous Serial Port Enable bit |
| CKP | 4 | Clock Polarity Select bit |
| SSPM | 3:0 | Synchronous Serial Port Mode Select bits |
SSP1CON2
- Address
0x791- Reset
0x00- Access
- read/write
- 7GCEN
- 6ACKSTAT
- 5ACKDT
- 4ACKEN
- 3RCEN
- 2PEN
- 1RSEN
- 0SEN
8 fields
| Field | Bits | What it does |
|---|---|---|
| GCEN | 7 | General Call Enable bit (Slave mode only) |
| ACKSTAT | 6 | Acknowledge Status bit (Transmission only) |
| ACKDT | 5 | Acknowledge Data bit (Receive mode only) |
| ACKEN | 4 | Acknowledge Sequence Enable bit (Master Receive mode only) |
| RCEN | 3 | Receive Enable bit (Master mode only) |
| PEN | 2 | Stop Condition Enable bit (Master mode only) |
| RSEN | 1 | Repeated Start Condition Enable bit (Master mode only) |
| SEN | 0 | Start Condition Enable/Stretch Enable bit |
SSP1CON3
- Address
0x792- Reset
0x00- Access
- read/write
- 7ACKTIM
- 6PCIE
- 5SCIE
- 4BOEN
- 3SDAHT
- 2SBCDE
- 1AHEN
- 0DHEN
8 fields
| Field | Bits | What it does |
|---|---|---|
| ACKTIM | 7 | |
| PCIE | 6 | |
| SCIE | 5 | |
| BOEN | 4 | |
| SDAHT | 3 | |
| SBCDE | 2 | |
| AHEN | 1 | |
| DHEN | 0 |
SSP2BUF
- Address
0x796- Reset
x (not fixed at power-on)- Access
- read/write
- 7SSPBUF7
- 6SSPBUF6
- 5SSPBUF5
- 4SSPBUF4
- 3SSPBUF3
- 2SSPBUF2
- 1SSPBUF1
- 0SSPBUF0
1 field
| Field | Bits | What it does |
|---|---|---|
| SSPBUF | 7:0 |
SSP2ADD
- Address
0x797- Reset
0x00- Access
- read/write
- 7SSPADD7
- 6SSPADD6
- 5SSPADD5
- 4SSPADD4
- 3SSPADD3
- 2SSPADD2
- 1SSPADD1
- 0SSPADD0
1 field
| Field | Bits | What it does |
|---|---|---|
| SSPADD | 7:0 |
SSP2MSK
- Address
0x798- Reset
0xFF- Access
- read/write
- 7SSPMSK7
- 6SSPMSK6
- 5SSPMSK5
- 4SSPMSK4
- 3SSPMSK3
- 2SSPMSK2
- 1SSPMSK1
- 0SSPMSK0
1 field
| Field | Bits | What it does |
|---|---|---|
| SSPMSK | 7:0 |
SSP2STATMSSP2 STATUS REGISTER
- Address
0x799- Reset
0x00- Access
- read/write
- 7SMP
- 6CKE
- 5D_nA
- 4P
- 3S
- 2R_nW
- 1UA
- 0BF
8 fields
| Field | Bits | What it does |
|---|---|---|
| SMP | 7 | SPI Data Input Sample Phase bit |
| CKE | 6 | SPI Clock Edge Select bit |
| D_nA | 5 | Data/Address bit |
| P | 4 | Stop bit |
| S | 3 | Start bit |
| R_nW | 2 | Read/Write Information bit |
| UA | 1 | Update Address bit |
| BF | 0 | Buffer Full Status bit (Receive mode only) |
SSP2CON1
- Address
0x79A- Reset
0x00- Access
- read/write
- 7WCOL
- 6SSPOV
- 5SSPEN
- 4CKP
- 3SSPM3
- 2SSPM2
- 1SSPM1
- 0SSPM0
5 fields
| Field | Bits | What it does |
|---|---|---|
| WCOL | 7 | Write Collision Detect bit (Transmit mode only) |
| SSPOV | 6 | Receive Overflow Indicator bit |
| SSPEN | 5 | Synchronous Serial Port Enable bit |
| CKP | 4 | Clock Polarity Select bit |
| SSPM | 3:0 | Synchronous Serial Port Mode Select bits |
SSP2CON2
- Address
0x79B- Reset
0x00- Access
- read/write
- 7GCEN
- 6ACKSTAT
- 5ACKDT
- 4ACKEN
- 3RCEN
- 2PEN
- 1RSEN
- 0SEN
8 fields
| Field | Bits | What it does |
|---|---|---|
| GCEN | 7 | General Call Enable bit (Slave mode only) |
| ACKSTAT | 6 | Acknowledge Status bit (Transmission only) |
| ACKDT | 5 | Acknowledge Data bit (Receive mode only) |
| ACKEN | 4 | Acknowledge Sequence Enable bit (Master Receive mode only) |
| RCEN | 3 | Receive Enable bit (Master mode only) |
| PEN | 2 | Stop Condition Enable bit (Master mode only) |
| RSEN | 1 | Repeated Start Condition Enable bit (Master mode only) |
| SEN | 0 | Start Condition Enable/Stretch Enable bit |
SSP2CON3
- Address
0x79C- Reset
0x00- Access
- read/write
- 7ACKTIM
- 6PCIE
- 5SCIE
- 4BOEN
- 3SDAHT
- 2SBCDE
- 1AHEN
- 0DHEN
8 fields
| Field | Bits | What it does |
|---|---|---|
| ACKTIM | 7 | |
| PCIE | 6 | |
| SCIE | 5 | |
| BOEN | 4 | |
| SDAHT | 3 | |
| SBCDE | 2 | |
| AHEN | 1 | |
| DHEN | 0 |
SSP1CLKPPS
- Address
0x1E47- Reset
0x13- Access
- read/write
- 7–
- 6SSP1CLKPPS6
- 5SSP1CLKPPS5
- 4SSP1CLKPPS4
- 3SSP1CLKPPS3
- 2SSP1CLKPPS2
- 1SSP1CLKPPS1
- 0SSP1CLKPPS0
1 field
| Field | Bits | What it does |
|---|---|---|
| SSP1CLKPPS | 6:0 |
SSP1DATPPS
- Address
0x1E48- Reset
0x14- Access
- read/write
- 7–
- 6SSP1DATPPS6
- 5SSP1DATPPS5
- 4SSP1DATPPS4
- 3SSP1DATPPS3
- 2SSP1DATPPS2
- 1SSP1DATPPS1
- 0SSP1DATPPS0
1 field
| Field | Bits | What it does |
|---|---|---|
| SSP1DATPPS | 6:0 |
SSP1SSPPS
- Address
0x1E49- Reset
0x05- Access
- read/write
- 7–
- 6SSP1SSPPS6
- 5SSP1SSPPS5
- 4SSP1SSPPS4
- 3SSP1SSPPS3
- 2SSP1SSPPS2
- 1SSP1SSPPS1
- 0SSP1SSPPS0
1 field
| Field | Bits | What it does |
|---|---|---|
| SSP1SSPPS | 6:0 |
SSP2CLKPPS
- Address
0x1E4A- Reset
0x09- Access
- read/write
- 7–
- 6SSP2CLKPPS6
- 5SSP2CLKPPS5
- 4SSP2CLKPPS4
- 3SSP2CLKPPS3
- 2SSP2CLKPPS2
- 1SSP2CLKPPS1
- 0SSP2CLKPPS0
1 field
| Field | Bits | What it does |
|---|---|---|
| SSP2CLKPPS | 6:0 |
SSP2DATPPS
- Address
0x1E4B- Reset
0x0A- Access
- read/write
- 7–
- 6SSP2DATPPS6
- 5SSP2DATPPS5
- 4SSP2DATPPS4
- 3SSP2DATPPS3
- 2SSP2DATPPS2
- 1SSP2DATPPS1
- 0SSP2DATPPS0
1 field
| Field | Bits | What it does |
|---|---|---|
| SSP2DATPPS | 6:0 |
SSP2SSPPS
- Address
0x1E4C- Reset
0x08- Access
- read/write
- 7–
- 6SSP2SSPPS6
- 5SSP2SSPPS5
- 4SSP2SSPPS4
- 3SSP2SSPPS3
- 2SSP2SSPPS2
- 1SSP2SSPPS1
- 0SSP2SSPPS0
1 field
| Field | Bits | What it does |
|---|---|---|
| SSP2SSPPS | 6:0 |