BETACLCDATA
- Address
0xF0F- Reset
x (not fixed at power-on)- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3MLC4OUT
- 2MCLC3OUT
- 1MCLC2OUT
- 0MCLC1OUT
4 fields
| Field | Bits | What it does |
|---|---|---|
| MLC4OUT | 3 | |
| MCLC3OUT | 2 | |
| MCLC2OUT | 1 | |
| MCLC1OUT | 0 |
PIC16LF1773 CLC registers
The 41 registers of CLC (Configurable logic cell ), from 0xF0F, with their reset value and every field. The PIC16LF1773 has 473 registers in 54 peripherals, one page each.
CLC Configurable logic cell
CLC1CONConfigurable logic cell control
- Address
0xF10- Reset
0x00- Access
- read/write
- 7LC1EN
- 6–
- 5LC1OUT
- 4LC1INTP
- 3LC1INTN
- 2LC1MODE2
- 1LC1MODE1
- 0LC1MODE0
5 fields
| Field | Bits | What it does |
|---|---|---|
| LC1EN | 7 | |
| LC1OUT | 5 | |
| LC1INTP | 4 | |
| LC1INTN | 3 | |
| LC1MODE | 2:0 |
CLC1POLPolarity control
- Address
0xF11- Reset
x (not fixed at power-on)- Access
- read/write
- 7LC1POL
- 6–
- 5–
- 4–
- 3LC1G4POL
- 2LC1G3POL
- 1LC1G2POL
- 0LC1G1POL
5 fields
| Field | Bits | What it does |
|---|---|---|
| LC1POL | 7 | |
| LC1G4POL | 3 | |
| LC1G3POL | 2 | |
| LC1G2POL | 1 | |
| LC1G1POL | 0 |
CLC1SEL0Input select register 1
- Address
0xF12- Reset
x (not fixed at power-on)- Access
- read/write
- 7–
- 6–
- 5LC1D1S5
- 4LC1D1S4
- 3LC1D1S3
- 2LC1D1S2
- 1LC1D1S1
- 0LC1D1S0
1 field
| Field | Bits | What it does |
|---|---|---|
| LC1D1S | 5:0 |
CLC1SEL1Input select register 1
- Address
0xF13- Reset
x (not fixed at power-on)- Access
- read/write
- 7–
- 6–
- 5LC1D2S5
- 4LC1D2S4
- 3LC1D2S3
- 2LC1D2S2
- 1LC1D2S1
- 0LC1D2S0
1 field
| Field | Bits | What it does |
|---|---|---|
| LC1D2S | 5:0 |
CLC1SEL2Input select register 2
- Address
0xF14- Reset
x (not fixed at power-on)- Access
- read/write
- 7–
- 6–
- 5LC1D3S5
- 4LC1D3S4
- 3LC1D3S3
- 2LC1D3S2
- 1LC1D3S1
- 0LC1D3S0
1 field
| Field | Bits | What it does |
|---|---|---|
| LC1D3S | 5:0 |
CLC1SEL3Input select register 3
- Address
0xF15- Reset
x (not fixed at power-on)- Access
- read/write
- 7–
- 6–
- 5LC1D4S5
- 4LC1D4S4
- 3LC1D4S3
- 2LC1D4S2
- 1LC1D4S1
- 0LC1D4S0
1 field
| Field | Bits | What it does |
|---|---|---|
| LC1D4S | 5:0 |
CLC1GLS0Gate logic select register 0
- Address
0xF16- Reset
x (not fixed at power-on)- Access
- read/write
- 7LC1G1D4T
- 6LC1G1D4N
- 5LC1G1D3T
- 4LC1G1D3N
- 3LC1G1D2T
- 2LC1G1D2N
- 1LC1G1D1T
- 0LC1G1D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| LC1G1D4T | 7 | |
| LC1G1D4N | 6 | |
| LC1G1D3T | 5 | |
| LC1G1D3N | 4 | |
| LC1G1D2T | 3 | |
| LC1G1D2N | 2 | |
| LC1G1D1T | 1 | |
| LC1G1D1N | 0 |
CLC1GLS1Gate logic select register 1
- Address
0xF17- Reset
x (not fixed at power-on)- Access
- read/write
- 7LC1G2D4T
- 6LC1G2D4N
- 5LC1G2D3T
- 4LC1G2D3N
- 3LC1G2D2T
- 2LC1G2D2N
- 1LC1G2D1T
- 0LC1G2D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| LC1G2D4T | 7 | |
| LC1G2D4N | 6 | |
| LC1G2D3T | 5 | |
| LC1G2D3N | 4 | |
| LC1G2D2T | 3 | |
| LC1G2D2N | 2 | |
| LC1G2D1T | 1 | |
| LC1G2D1N | 0 |
CLC1GLS2Gate logic select register 2
- Address
0xF18- Reset
x (not fixed at power-on)- Access
- read/write
- 7LC1G3D4T
- 6LC1G3D4N
- 5LC1G3D3T
- 4LC1G3D3N
- 3LC1G3D2T
- 2LC1G3D2N
- 1LC1G3D1T
- 0LC1G3D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| LC1G3D4T | 7 | |
| LC1G3D4N | 6 | |
| LC1G3D3T | 5 | |
| LC1G3D3N | 4 | |
| LC1G3D2T | 3 | |
| LC1G3D2N | 2 | |
| LC1G3D1T | 1 | |
| LC1G3D1N | 0 |
CLC1GLS3Gate logic select register 3
- Address
0xF19- Reset
x (not fixed at power-on)- Access
- read/write
- 7LC1G4D4T
- 6LC1G4D4N
- 5LC1G4D3T
- 4LC1G4D3N
- 3LC1G4D2T
- 2LC1G4D2N
- 1LC1G4D1T
- 0LC1G4D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| LC1G4D4T | 7 | |
| LC1G4D4N | 6 | |
| LC1G4D3T | 5 | |
| LC1G4D3N | 4 | |
| LC1G4D2T | 3 | |
| LC1G4D2N | 2 | |
| LC1G4D1T | 1 | |
| LC1G4D1N | 0 |
CLC2CONConfigurable logic cell control
- Address
0xF1A- Reset
0x00- Access
- read/write
- 7LC2EN
- 6–
- 5LC2OUT
- 4LC2INTP
- 3LC2INTN
- 2LC2MODE2
- 1LC2MODE1
- 0LC2MODE0
5 fields
| Field | Bits | What it does |
|---|---|---|
| LC2EN | 7 | |
| LC2OUT | 5 | |
| LC2INTP | 4 | |
| LC2INTN | 3 | |
| LC2MODE | 2:0 |
CLC2POLPolarity control
- Address
0xF1B- Reset
x (not fixed at power-on)- Access
- read/write
- 7LC2POL
- 6–
- 5–
- 4–
- 3LC2G4POL
- 2LC2G3POL
- 1LC2G2POL
- 0LC2G1POL
5 fields
| Field | Bits | What it does |
|---|---|---|
| LC2POL | 7 | |
| LC2G4POL | 3 | |
| LC2G3POL | 2 | |
| LC2G2POL | 1 | |
| LC2G1POL | 0 |
CLC2SEL0Input select register 1
- Address
0xF1C- Reset
x (not fixed at power-on)- Access
- read/write
- 7–
- 6–
- 5LC2D1S5
- 4LC2D1S4
- 3LC2D1S3
- 2LC2D1S2
- 1LC2D1S1
- 0LC2D1S0
1 field
| Field | Bits | What it does |
|---|---|---|
| LC2D1S | 5:0 |
CLC2SEL1Input select register 1
- Address
0xF1D- Reset
x (not fixed at power-on)- Access
- read/write
- 7–
- 6–
- 5LC2D2S5
- 4LC2D2S4
- 3LC2D2S3
- 2LC2D2S2
- 1LC2D2S1
- 0LC2D2S0
1 field
| Field | Bits | What it does |
|---|---|---|
| LC2D2S | 5:0 |
CLC2SEL2Input select register 2
- Address
0xF1E- Reset
x (not fixed at power-on)- Access
- read/write
- 7–
- 6–
- 5LC2D3S5
- 4LC2D3S4
- 3LC2D3S3
- 2LC2D3S2
- 1LC2D3S1
- 0LC2D3S0
1 field
| Field | Bits | What it does |
|---|---|---|
| LC2D3S | 5:0 |
CLC2SEL3Input select register 3
- Address
0xF1F- Reset
x (not fixed at power-on)- Access
- read/write
- 7–
- 6–
- 5LC2D4S5
- 4LC2D4S4
- 3LC2D4S3
- 2LC2D4S2
- 1LC2D4S1
- 0LC2D4S0
1 field
| Field | Bits | What it does |
|---|---|---|
| LC2D4S | 5:0 |
CLC2GLS0Gate logic select register 0
- Address
0xF20- Reset
x (not fixed at power-on)- Access
- read/write
- 7LC2G1D4T
- 6LC2G1D4N
- 5LC2G1D3T
- 4LC2G1D3N
- 3LC2G1D2T
- 2LC2G1D2N
- 1LC2G1D1T
- 0LC2G1D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| LC2G1D4T | 7 | |
| LC2G1D4N | 6 | |
| LC2G1D3T | 5 | |
| LC2G1D3N | 4 | |
| LC2G1D2T | 3 | |
| LC2G1D2N | 2 | |
| LC2G1D1T | 1 | |
| LC2G1D1N | 0 |
CLC2GLS1Gate logic select register 1
- Address
0xF21- Reset
x (not fixed at power-on)- Access
- read/write
- 7LC2G2D4T
- 6LC2G2D4N
- 5LC2G2D3T
- 4LC2G2D3N
- 3LC2G2D2T
- 2LC2G2D2N
- 1LC2G2D1T
- 0LC2G2D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| LC2G2D4T | 7 | |
| LC2G2D4N | 6 | |
| LC2G2D3T | 5 | |
| LC2G2D3N | 4 | |
| LC2G2D2T | 3 | |
| LC2G2D2N | 2 | |
| LC2G2D1T | 1 | |
| LC2G2D1N | 0 |
CLC2GLS2Gate logic select register 2
- Address
0xF22- Reset
x (not fixed at power-on)- Access
- read/write
- 7LC2G3D4T
- 6LC2G3D4N
- 5LC2G3D3T
- 4LC2G3D3N
- 3LC2G3D2T
- 2LC2G3D2N
- 1LC2G3D1T
- 0LC2G3D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| LC2G3D4T | 7 | |
| LC2G3D4N | 6 | |
| LC2G3D3T | 5 | |
| LC2G3D3N | 4 | |
| LC2G3D2T | 3 | |
| LC2G3D2N | 2 | |
| LC2G3D1T | 1 | |
| LC2G3D1N | 0 |
CLC2GLS3Gate logic select register 3
- Address
0xF23- Reset
x (not fixed at power-on)- Access
- read/write
- 7LC2G4D4T
- 6LC2G4D4N
- 5LC2G4D3T
- 4LC2G4D3N
- 3LC2G4D2T
- 2LC2G4D2N
- 1LC2G4D1T
- 0LC2G4D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| LC2G4D4T | 7 | |
| LC2G4D4N | 6 | |
| LC2G4D3T | 5 | |
| LC2G4D3N | 4 | |
| LC2G4D2T | 3 | |
| LC2G4D2N | 2 | |
| LC2G4D1T | 1 | |
| LC2G4D1N | 0 |
CLC3CONConfigurable logic cell control
- Address
0xF24- Reset
0x00- Access
- read/write
- 7LC3EN
- 6–
- 5LC3OUT
- 4LC3INTP
- 3LC3INTN
- 2LC3MODE2
- 1LC3MODE1
- 0LC3MODE0
5 fields
| Field | Bits | What it does |
|---|---|---|
| LC3EN | 7 | |
| LC3OUT | 5 | |
| LC3INTP | 4 | |
| LC3INTN | 3 | |
| LC3MODE | 2:0 |
CLC3POLPolarity control
- Address
0xF25- Reset
x (not fixed at power-on)- Access
- read/write
- 7LC3POL
- 6–
- 5–
- 4–
- 3LC3G4POL
- 2LC3G3POL
- 1LC3G2POL
- 0LC3G1POL
5 fields
| Field | Bits | What it does |
|---|---|---|
| LC3POL | 7 | |
| LC3G4POL | 3 | |
| LC3G3POL | 2 | |
| LC3G2POL | 1 | |
| LC3G1POL | 0 |
CLC3SEL0Input select register 1
- Address
0xF26- Reset
x (not fixed at power-on)- Access
- read/write
- 7–
- 6–
- 5LC3D1S5
- 4LC3D1S4
- 3LC3D1S3
- 2LC3D1S2
- 1LC3D1S1
- 0LC3D1S0
1 field
| Field | Bits | What it does |
|---|---|---|
| LC3D1S | 5:0 |
CLC3SEL1Input select register 1
- Address
0xF27- Reset
x (not fixed at power-on)- Access
- read/write
- 7–
- 6–
- 5LC3D2S5
- 4LC3D2S4
- 3LC3D2S3
- 2LC3D2S2
- 1LC3D2S1
- 0LC3D2S0
1 field
| Field | Bits | What it does |
|---|---|---|
| LC3D2S | 5:0 |
CLC3SEL2Input select register 2
- Address
0xF28- Reset
x (not fixed at power-on)- Access
- read/write
- 7–
- 6–
- 5LC3D3S5
- 4LC3D3S4
- 3LC3D3S3
- 2LC3D3S2
- 1LC3D3S1
- 0LC3D3S0
1 field
| Field | Bits | What it does |
|---|---|---|
| LC3D3S | 5:0 |
CLC3SEL3Input select register 3
- Address
0xF29- Reset
x (not fixed at power-on)- Access
- read/write
- 7–
- 6–
- 5LC3D4S5
- 4LC3D4S4
- 3LC3D4S3
- 2LC3D4S2
- 1LC3D4S1
- 0LC3D4S0
1 field
| Field | Bits | What it does |
|---|---|---|
| LC3D4S | 5:0 |
CLC3GLS0Gate logic select register 0
- Address
0xF2A- Reset
x (not fixed at power-on)- Access
- read/write
- 7LC3G1D4T
- 6LC3G1D4N
- 5LC3G1D3T
- 4LC3G1D3N
- 3LC3G1D2T
- 2LC3G1D2N
- 1LC3G1D1T
- 0LC3G1D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| LC3G1D4T | 7 | |
| LC3G1D4N | 6 | |
| LC3G1D3T | 5 | |
| LC3G1D3N | 4 | |
| LC3G1D2T | 3 | |
| LC3G1D2N | 2 | |
| LC3G1D1T | 1 | |
| LC3G1D1N | 0 |
CLC3GLS1Gate logic select register 1
- Address
0xF2B- Reset
x (not fixed at power-on)- Access
- read/write
- 7LC3G2D4T
- 6LC3G2D4N
- 5LC3G2D3T
- 4LC3G2D3N
- 3LC3G2D2T
- 2LC3G2D2N
- 1LC3G2D1T
- 0LC3G2D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| LC3G2D4T | 7 | |
| LC3G2D4N | 6 | |
| LC3G2D3T | 5 | |
| LC3G2D3N | 4 | |
| LC3G2D2T | 3 | |
| LC3G2D2N | 2 | |
| LC3G2D1T | 1 | |
| LC3G2D1N | 0 |
CLC3GLS2Gate logic select register 2
- Address
0xF2C- Reset
x (not fixed at power-on)- Access
- read/write
- 7LC3G3D4T
- 6LC3G3D4N
- 5LC3G3D3T
- 4LC3G3D3N
- 3LC3G3D2T
- 2LC3G3D2N
- 1LC3G3D1T
- 0LC3G3D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| LC3G3D4T | 7 | |
| LC3G3D4N | 6 | |
| LC3G3D3T | 5 | |
| LC3G3D3N | 4 | |
| LC3G3D2T | 3 | |
| LC3G3D2N | 2 | |
| LC3G3D1T | 1 | |
| LC3G3D1N | 0 |
CLC3GLS3Gate logic select register 3
- Address
0xF2D- Reset
x (not fixed at power-on)- Access
- read/write
- 7LC3G4D4T
- 6LC3G4D4N
- 5LC3G4D3T
- 4LC3G4D3N
- 3LC3G4D2T
- 2LC3G4D2N
- 1LC3G4D1T
- 0LC3G4D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| LC3G4D4T | 7 | |
| LC3G4D4N | 6 | |
| LC3G4D3T | 5 | |
| LC3G4D3N | 4 | |
| LC3G4D2T | 3 | |
| LC3G4D2N | 2 | |
| LC3G4D1T | 1 | |
| LC3G4D1N | 0 |
CLC4CONConfigurable logic cell control
- Address
0xF2E- Reset
0x00- Access
- read/write
- 7LC4EN
- 6–
- 5LC4OUT
- 4LC4INTP
- 3LC4INTN
- 2LC4MODE2
- 1LC4MODE1
- 0LC4MODE0
5 fields
| Field | Bits | What it does |
|---|---|---|
| LC4EN | 7 | |
| LC4OUT | 5 | |
| LC4INTP | 4 | |
| LC4INTN | 3 | |
| LC4MODE | 2:0 |
CLC4POLPolarity control
- Address
0xF2F- Reset
x (not fixed at power-on)- Access
- read/write
- 7LC4POL
- 6–
- 5–
- 4–
- 3LC4G4POL
- 2LC4G3POL
- 1LC4G2POL
- 0LC4G1POL
5 fields
| Field | Bits | What it does |
|---|---|---|
| LC4POL | 7 | |
| LC4G4POL | 3 | |
| LC4G3POL | 2 | |
| LC4G2POL | 1 | |
| LC4G1POL | 0 |
CLC4SEL0Input select register 1
- Address
0xF30- Reset
x (not fixed at power-on)- Access
- read/write
- 7–
- 6–
- 5LC4D1S5
- 4LC4D1S4
- 3LC4D1S3
- 2LC4D1S2
- 1LC4D1S1
- 0LC4D1S0
1 field
| Field | Bits | What it does |
|---|---|---|
| LC4D1S | 5:0 |
CLC4SEL1Input select register 1
- Address
0xF31- Reset
x (not fixed at power-on)- Access
- read/write
- 7–
- 6–
- 5LC4D2S5
- 4LC4D2S4
- 3LC4D2S3
- 2LC4D2S2
- 1LC4D2S1
- 0LC4D2S0
1 field
| Field | Bits | What it does |
|---|---|---|
| LC4D2S | 5:0 |
CLC4SEL2Input select register 2
- Address
0xF32- Reset
x (not fixed at power-on)- Access
- read/write
- 7–
- 6–
- 5LC4D3S5
- 4LC4D3S4
- 3LC4D3S3
- 2LC4D3S2
- 1LC4D3S1
- 0LC4D3S0
1 field
| Field | Bits | What it does |
|---|---|---|
| LC4D3S | 5:0 |
CLC4SEL3Input select register 3
- Address
0xF33- Reset
x (not fixed at power-on)- Access
- read/write
- 7–
- 6–
- 5LC4D4S5
- 4LC4D4S4
- 3LC4D4S3
- 2LC4D4S2
- 1LC4D4S1
- 0LC4D4S0
1 field
| Field | Bits | What it does |
|---|---|---|
| LC4D4S | 5:0 |
CLC4GLS0Gate logic select register 0
- Address
0xF34- Reset
x (not fixed at power-on)- Access
- read/write
- 7LC4G1D4T
- 6LC4G1D4N
- 5LC4G1D3T
- 4LC4G1D3N
- 3LC4G1D2T
- 2LC4G1D2N
- 1LC4G1D1T
- 0LC4G1D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| LC4G1D4T | 7 | |
| LC4G1D4N | 6 | |
| LC4G1D3T | 5 | |
| LC4G1D3N | 4 | |
| LC4G1D2T | 3 | |
| LC4G1D2N | 2 | |
| LC4G1D1T | 1 | |
| LC4G1D1N | 0 |
CLC4GLS1Gate logic select register 1
- Address
0xF35- Reset
x (not fixed at power-on)- Access
- read/write
- 7LC4G2D4T
- 6LC4G2D4N
- 5LC4G2D3T
- 4LC4G2D3N
- 3LC4G2D2T
- 2LC4G2D2N
- 1LC4G2D1T
- 0LC4G2D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| LC4G2D4T | 7 | |
| LC4G2D4N | 6 | |
| LC4G2D3T | 5 | |
| LC4G2D3N | 4 | |
| LC4G2D2T | 3 | |
| LC4G2D2N | 2 | |
| LC4G2D1T | 1 | |
| LC4G2D1N | 0 |
CLC4GLS2Gate logic select register 2
- Address
0xF36- Reset
x (not fixed at power-on)- Access
- read/write
- 7LC4G3D4T
- 6LC4G3D4N
- 5LC4G3D3T
- 4LC4G3D3N
- 3LC4G3D2T
- 2LC4G3D2N
- 1LC4G3D1T
- 0LC4G3D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| LC4G3D4T | 7 | |
| LC4G3D4N | 6 | |
| LC4G3D3T | 5 | |
| LC4G3D3N | 4 | |
| LC4G3D2T | 3 | |
| LC4G3D2N | 2 | |
| LC4G3D1T | 1 | |
| LC4G3D1N | 0 |
CLC4GLS3Gate logic select register 3
- Address
0xF37- Reset
x (not fixed at power-on)- Access
- read/write
- 7LC4G4D4T
- 6LC4G4D4N
- 5LC4G4D3T
- 4LC4G4D3N
- 3LC4G4D2T
- 2LC4G4D2N
- 1LC4G4D1T
- 0LC4G4D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| LC4G4D4T | 7 | |
| LC4G4D4N | 6 | |
| LC4G4D3T | 5 | |
| LC4G4D3N | 4 | |
| LC4G4D2T | 3 | |
| LC4G4D2N | 2 | |
| LC4G4D1T | 1 | |
| LC4G4D1N | 0 |