BETASSP2CLKPPS
- Address
0xE8A- Reset
0x09- Access
- read/write
- 7–
- 6–
- 5–
- 4PORT1
- 3PORT0
- 2PIN2
- 1PIN1
- 0PIN0
2 fields
| Field | Bits | What it does |
|---|---|---|
| PORT | 4:3 | |
| PIN | 2:0 |
PIC18F46Q10 MSSP registers
The 20 registers of MSSP (Master synchronous serial port (SPI, I²C)), from 0xE8A, with their reset value and every field. The PIC18F46Q10 has 462 registers in 38 peripherals, one page each.
MSSP Master synchronous serial port (SPI, I²C)
SSP2DATPPS
- Address
0xE8B- Reset
0x0A- Access
- read/write
- 7–
- 6–
- 5–
- 4PORT1
- 3PORT0
- 2PIN2
- 1PIN1
- 0PIN0
2 fields
| Field | Bits | What it does |
|---|---|---|
| PORT | 4:3 | |
| PIN | 2:0 |
SSP2SSPPS
- Address
0xE8C- Reset
0x08- Access
- read/write
- 7–
- 6–
- 5–
- 4PORT1
- 3PORT0
- 2PIN2
- 1PIN1
- 0PIN0
2 fields
| Field | Bits | What it does |
|---|---|---|
| PORT | 4:3 | |
| PIN | 2:0 |
SSP2BUF
- Address
0xE8D- Reset
x (not fixed at power-on)- Access
- read/write
- 7SSPBUF7
- 6SSPBUF6
- 5SSPBUF5
- 4SSPBUF4
- 3SSPBUF3
- 2SSPBUF2
- 1SSPBUF1
- 0SSPBUF0
1 field
| Field | Bits | What it does |
|---|---|---|
| SSPBUF | 7:0 |
SSP2ADD
- Address
0xE8E- Reset
0x00- Access
- read/write
- 7SSPADD7
- 6SSPADD6
- 5SSPADD5
- 4SSPADD4
- 3SSPADD3
- 2SSPADD2
- 1SSPADD1
- 0SSPADD0
1 field
| Field | Bits | What it does |
|---|---|---|
| SSPADD | 7:0 |
SSP2MSK
- Address
0xE8F- Reset
0xFF- Access
- read/write
- 7SSPMSK7
- 6SSPMSK6
- 5SSPMSK5
- 4SSPMSK4
- 3SSPMSK3
- 2SSPMSK2
- 1SSPMSK1
- 0SSPMSK0
1 field
| Field | Bits | What it does |
|---|---|---|
| SSPMSK | 7:0 |
SSP2STATMSSP2 STATUS REGISTER
- Address
0xE90- Reset
0x00- Access
- read/write
- 7SMP
- 6CKE
- 5D_nA
- 4P
- 3S
- 2R_nW
- 1UA
- 0BF
8 fields
| Field | Bits | What it does |
|---|---|---|
| SMP | 7 | SPI Data Input Sample Phase bit |
| CKE | 6 | SPI Clock Edge Select bit |
| D_nA | 5 | Data/Address bit |
| P | 4 | Stop bit |
| S | 3 | Start bit |
| R_nW | 2 | Read/Write Information bit |
| UA | 1 | Update Address bit |
| BF | 0 | Buffer Full Status bit (Receive mode only) |
SSP2CON1
- Address
0xE91- Reset
0x00- Access
- read/write
- 7WCOL
- 6SSPOV
- 5SSPEN
- 4CKP
- 3SSPM3
- 2SSPM2
- 1SSPM1
- 0SSPM0
5 fields
| Field | Bits | What it does |
|---|---|---|
| WCOL | 7 | Write Collision Detect bit (Transmit mode only) |
| SSPOV | 6 | Receive Overflow Indicator bit |
| SSPEN | 5 | Synchronous Serial Port Enable bit |
| CKP | 4 | Clock Polarity Select bit |
| SSPM | 3:0 | Synchronous Serial Port Mode Select bits |
SSP2CON2
- Address
0xE92- Reset
0x00- Access
- read/write
- 7GCEN
- 6ACKSTAT
- 5ACKDT
- 4ACKEN
- 3RCEN
- 2PEN
- 1RSEN
- 0SEN
8 fields
| Field | Bits | What it does |
|---|---|---|
| GCEN | 7 | General Call Enable bit (Slave mode only) |
| ACKSTAT | 6 | Acknowledge Status bit (Transmission only) |
| ACKDT | 5 | Acknowledge Data bit (Receive mode only) |
| ACKEN | 4 | Acknowledge Sequence Enable bit (Master Receive mode only) |
| RCEN | 3 | Receive Enable bit (Master mode only) |
| PEN | 2 | Stop Condition Enable bit (Master mode only) |
| RSEN | 1 | Repeated Start Condition Enable bit (Master mode only) |
| SEN | 0 | Start Condition Enable/Stretch Enable bit |
SSP2CON3
- Address
0xE93- Reset
0x00- Access
- read/write
- 7ACKTIM
- 6PCIE
- 5SCIE
- 4BOEN
- 3SDAHT
- 2SBCDE
- 1AHEN
- 0DHEN
8 fields
| Field | Bits | What it does |
|---|---|---|
| ACKTIM | 7 | |
| PCIE | 6 | |
| SCIE | 5 | |
| BOEN | 4 | |
| SDAHT | 3 | |
| SBCDE | 2 | |
| AHEN | 1 | |
| DHEN | 0 |
SSP1CLKPPS
- Address
0xEB2- Reset
0x13- Access
- read/write
- 7–
- 6–
- 5–
- 4PORT1
- 3PORT0
- 2PIN2
- 1PIN1
- 0PIN0
2 fields
| Field | Bits | What it does |
|---|---|---|
| PORT | 4:3 | |
| PIN | 2:0 |
SSP1DATPPS
- Address
0xEB3- Reset
0x14- Access
- read/write
- 7–
- 6–
- 5–
- 4PORT1
- 3PORT0
- 2PIN2
- 1PIN1
- 0PIN0
2 fields
| Field | Bits | What it does |
|---|---|---|
| PORT | 4:3 | |
| PIN | 2:0 |
SSP1SSPPS
- Address
0xEB4- Reset
0x05- Access
- read/write
- 7–
- 6–
- 5–
- 4PORT1
- 3PORT0
- 2PIN2
- 1PIN1
- 0PIN0
2 fields
| Field | Bits | What it does |
|---|---|---|
| PORT | 4:3 | |
| PIN | 2:0 |
SSP1BUF
- Address
0xF91- Reset
x (not fixed at power-on)- Access
- read/write
- 7SSPBUF7
- 6SSPBUF6
- 5SSPBUF5
- 4SSPBUF4
- 3SSPBUF3
- 2SSPBUF2
- 1SSPBUF1
- 0SSPBUF0
1 field
| Field | Bits | What it does |
|---|---|---|
| SSPBUF | 7:0 |
SSP1ADD
- Address
0xF92- Reset
0x00- Access
- read/write
- 7SSPADD7
- 6SSPADD6
- 5SSPADD5
- 4SSPADD4
- 3SSPADD3
- 2SSPADD2
- 1SSPADD1
- 0SSPADD0
1 field
| Field | Bits | What it does |
|---|---|---|
| SSPADD | 7:0 |
SSP1MSK
- Address
0xF93- Reset
0xFF- Access
- read/write
- 7SSPMSK7
- 6SSPMSK6
- 5SSPMSK5
- 4SSPMSK4
- 3SSPMSK3
- 2SSPMSK2
- 1SSPMSK1
- 0SSPMSK0
1 field
| Field | Bits | What it does |
|---|---|---|
| SSPMSK | 7:0 |
SSP1STATMSSP1 STATUS REGISTER
- Address
0xF94- Reset
0x00- Access
- read/write
- 7SMP
- 6CKE
- 5D_nA
- 4P
- 3S
- 2R_nW
- 1UA
- 0BF
8 fields
| Field | Bits | What it does |
|---|---|---|
| SMP | 7 | SPI Data Input Sample Phase bit |
| CKE | 6 | SPI Clock Edge Select bit |
| D_nA | 5 | Data/Address bit |
| P | 4 | Stop bit |
| S | 3 | Start bit |
| R_nW | 2 | Read/Write Information bit |
| UA | 1 | Update Address bit |
| BF | 0 | Buffer Full Status bit (Receive mode only) |
SSP1CON1
- Address
0xF95- Reset
0x00- Access
- read/write
- 7WCOL
- 6SSPOV
- 5SSPEN
- 4CKP
- 3SSPM3
- 2SSPM2
- 1SSPM1
- 0SSPM0
5 fields
| Field | Bits | What it does |
|---|---|---|
| WCOL | 7 | Write Collision Detect bit (Transmit mode only) |
| SSPOV | 6 | Receive Overflow Indicator bit |
| SSPEN | 5 | Synchronous Serial Port Enable bit |
| CKP | 4 | Clock Polarity Select bit |
| SSPM | 3:0 | Synchronous Serial Port Mode Select bits |
SSP1CON2
- Address
0xF96- Reset
0x00- Access
- read/write
- 7GCEN
- 6ACKSTAT
- 5ACKDT
- 4ACKEN
- 3RCEN
- 2PEN
- 1RSEN
- 0SEN
8 fields
| Field | Bits | What it does |
|---|---|---|
| GCEN | 7 | General Call Enable bit (Slave mode only) |
| ACKSTAT | 6 | Acknowledge Status bit (Transmission only) |
| ACKDT | 5 | Acknowledge Data bit (Receive mode only) |
| ACKEN | 4 | Acknowledge Sequence Enable bit (Master Receive mode only) |
| RCEN | 3 | Receive Enable bit (Master mode only) |
| PEN | 2 | Stop Condition Enable bit (Master mode only) |
| RSEN | 1 | Repeated Start Condition Enable bit (Master mode only) |
| SEN | 0 | Start Condition Enable/Stretch Enable bit |
SSP1CON3
- Address
0xF97- Reset
0x00- Access
- read/write
- 7ACKTIM
- 6PCIE
- 5SCIE
- 4BOEN
- 3SDAHT
- 2SBCDE
- 1AHEN
- 0DHEN
8 fields
| Field | Bits | What it does |
|---|---|---|
| ACKTIM | 7 | |
| PCIE | 6 | |
| SCIE | 5 | |
| BOEN | 4 | |
| SDAHT | 3 | |
| SBCDE | 2 | |
| AHEN | 1 | |
| DHEN | 0 |