PIC18F96J94 ECCP registers The 6 registers of ECCP (Enhanced capture/compare/PWM ), from 0xF1B, with their reset value and every field. The PIC18F96J94 has 512 registers in 54 peripherals, one page each.
ECCP Enhanced capture/compare/PWM PSTR3CON
Address 0xF1B
Reset 0x01
Access read/write 7 CMPL1 6 CMPL0 5 – 4 STRSYNC 3 STRD 2 STRC 1 STRB 0 STRA 6 fields
Field Bits What it does CMPL 7:6 STRSYNC 4 STRD 3 STRC 2 STRB 1 STRA 0
PSTR2CON
Address 0xF1C
Reset 0x01
Access read/write 7 CMPL1 6 CMPL0 5 – 4 STRSYNC 3 STRD 2 STRC 1 STRB 0 STRA 6 fields
Field Bits What it does CMPL 7:6 STRSYNC 4 STRD 3 STRC 2 STRB 1 STRA 0
CCPTMRS2
Address 0xF34
Reset 0x00
Access read/write 7 – 6 – 5 – 4 C10TSEL 3 – 2 C9TSEL 1 C8TSEL1 0 C8TSEL0 3 fields
Field Bits What it does C10TSEL 4 C9TSEL 2 C8TSEL 1:0
CCPTMRS1
Address 0xF35
Reset 0x00
Access read/write 7 C7TSEL1 6 C7TSEL0 5 – 4 C6TSEL 3 – 2 C5TSEL 1 C4TSEL1 0 C4TSEL0 4 fields
Field Bits What it does C7TSEL 7:6 C6TSEL 4 C5TSEL 2 C4TSEL 1:0
CCPTMRS0
Address 0xF36
Reset 0x00
Access read/write 7 C3TSEL1 6 C3TSEL0 5 C2TSEL2 4 C2TSEL1 3 C2TSEL0 2 C1TSEL2 1 C1TSEL1 0 C1TSEL0 3 fields
Field Bits What it does C3TSEL 7:6 C2TSEL 5:3 C1TSEL 2:0
PSTR1CON
Address 0xF9C
Reset 0x01
Access read/write 7 CMPL1 6 CMPL0 5 – 4 STRSYNC 3 STRD 2 STRC 1 STRB 0 STRA 6 fields
Field Bits What it does CMPL 7:6 STRSYNC 4 STRD 3 STRC 2 STRB 1 STRA 0
BETA