BETACLC4CONConfigurable logic cell control
- Address
0x3C56- Reset
0x00- Access
- read/write
- 7EN
- 6OE
- 5OUT
- 4INTP
- 3INTN
- 2MODE2
- 1MODE1
- 0MODE0
6 fields
| Field | Bits | What it does |
|---|---|---|
| EN | 7 | |
| OE | 6 | |
| OUT | 5 | |
| INTP | 4 | |
| INTN | 3 | |
| MODE | 2:0 |
PIC18LF47K42 CLC registers
The 41 registers of CLC (Configurable logic cell ), from 0x3C56, with their reset value and every field. The PIC18LF47K42 has 634 registers in 54 peripherals, one page each.
CLC Configurable logic cell
CLC4POLPolarity control
- Address
0x3C57- Reset
x (not fixed at power-on)- Access
- read/write
- 7POL
- 6–
- 5–
- 4–
- 3G4POL
- 2G3POL
- 1G2POL
- 0G1POL
5 fields
| Field | Bits | What it does |
|---|---|---|
| POL | 7 | |
| G4POL | 3 | |
| G3POL | 2 | |
| G2POL | 1 | |
| G1POL | 0 |
CLC4SEL0Input select register 1
- Address
0x3C58- Reset
x (not fixed at power-on)- Access
- read/write
- 7D1S7
- 6D1S6
- 5D1S5
- 4D1S4
- 3D1S3
- 2D1S2
- 1D1S1
- 0D1S0
1 field
| Field | Bits | What it does |
|---|---|---|
| D1S | 7:0 |
CLC4SEL1Input select register 1
- Address
0x3C59- Reset
x (not fixed at power-on)- Access
- read/write
- 7D2S7
- 6D2S6
- 5D2S5
- 4D2S4
- 3D2S3
- 2D2S2
- 1D2S1
- 0D2S0
1 field
| Field | Bits | What it does |
|---|---|---|
| D2S | 7:0 |
CLC4SEL2Input select register 1
- Address
0x3C5A- Reset
x (not fixed at power-on)- Access
- read/write
- 7D3S7
- 6D3S6
- 5D3S5
- 4D3S4
- 3D3S3
- 2D3S2
- 1D3S1
- 0D3S0
1 field
| Field | Bits | What it does |
|---|---|---|
| D3S | 7:0 |
CLC4SEL3Input select register 1
- Address
0x3C5B- Reset
x (not fixed at power-on)- Access
- read/write
- 7D4S7
- 6D4S6
- 5D4S5
- 4D4S4
- 3D4S3
- 2D4S2
- 1D4S1
- 0D4S0
1 field
| Field | Bits | What it does |
|---|---|---|
| D4S | 7:0 |
CLC4GLS0Gate logic select register 0
- Address
0x3C5C- Reset
x (not fixed at power-on)- Access
- read/write
- 7G1D4T
- 6G1D4N
- 5G1D3T
- 4G1D3N
- 3G1D2T
- 2G1D2N
- 1G1D1T
- 0G1D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| G1D4T | 7 | |
| G1D4N | 6 | |
| G1D3T | 5 | |
| G1D3N | 4 | |
| G1D2T | 3 | |
| G1D2N | 2 | |
| G1D1T | 1 | |
| G1D1N | 0 |
CLC4GLS1Gate logic select register 1
- Address
0x3C5D- Reset
x (not fixed at power-on)- Access
- read/write
- 7G2D4T
- 6G2D4N
- 5G2D3T
- 4G2D3N
- 3G2D2T
- 2G2D2N
- 1G2D1T
- 0G2D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| G2D4T | 7 | |
| G2D4N | 6 | |
| G2D3T | 5 | |
| G2D3N | 4 | |
| G2D2T | 3 | |
| G2D2N | 2 | |
| G2D1T | 1 | |
| G2D1N | 0 |
CLC4GLS2Gate logic select register 2
- Address
0x3C5E- Reset
x (not fixed at power-on)- Access
- read/write
- 7G3D4T
- 6G3D4N
- 5G3D3T
- 4G3D3N
- 3G3D2T
- 2G3D2N
- 1G3D1T
- 0G3D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| G3D4T | 7 | |
| G3D4N | 6 | |
| G3D3T | 5 | |
| G3D3N | 4 | |
| G3D2T | 3 | |
| G3D2N | 2 | |
| G3D1T | 1 | |
| G3D1N | 0 |
CLC4GLS3Gate logic select register 3
- Address
0x3C5F- Reset
x (not fixed at power-on)- Access
- read/write
- 7G4D4T
- 6G4D4N
- 5G4D3T
- 4G4D3N
- 3G4D2T
- 2G4D2N
- 1G4D1T
- 0G4D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| G4D4T | 7 | |
| G4D4N | 6 | |
| G4D3T | 5 | |
| G4D3N | 4 | |
| G4D2T | 3 | |
| G4D2N | 2 | |
| G4D1T | 1 | |
| G4D1N | 0 |
CLC3CONConfigurable logic cell control
- Address
0x3C60- Reset
0x00- Access
- read/write
- 7EN
- 6OE
- 5OUT
- 4INTP
- 3INTN
- 2MODE2
- 1MODE1
- 0MODE0
6 fields
| Field | Bits | What it does |
|---|---|---|
| EN | 7 | |
| OE | 6 | |
| OUT | 5 | |
| INTP | 4 | |
| INTN | 3 | |
| MODE | 2:0 |
CLC3POLPolarity control
- Address
0x3C61- Reset
x (not fixed at power-on)- Access
- read/write
- 7POL
- 6–
- 5–
- 4–
- 3G4POL
- 2G3POL
- 1G2POL
- 0G1POL
5 fields
| Field | Bits | What it does |
|---|---|---|
| POL | 7 | |
| G4POL | 3 | |
| G3POL | 2 | |
| G2POL | 1 | |
| G1POL | 0 |
CLC3SEL0Input select register 1
- Address
0x3C62- Reset
x (not fixed at power-on)- Access
- read/write
- 7D1S7
- 6D1S6
- 5D1S5
- 4D1S4
- 3D1S3
- 2D1S2
- 1D1S1
- 0D1S0
1 field
| Field | Bits | What it does |
|---|---|---|
| D1S | 7:0 |
CLC3SEL1Input select register 1
- Address
0x3C63- Reset
x (not fixed at power-on)- Access
- read/write
- 7D2S7
- 6D2S6
- 5D2S5
- 4D2S4
- 3D2S3
- 2D2S2
- 1D2S1
- 0D2S0
1 field
| Field | Bits | What it does |
|---|---|---|
| D2S | 7:0 |
CLC3SEL2Input select register 1
- Address
0x3C64- Reset
x (not fixed at power-on)- Access
- read/write
- 7D3S7
- 6D3S6
- 5D3S5
- 4D3S4
- 3D3S3
- 2D3S2
- 1D3S1
- 0D3S0
1 field
| Field | Bits | What it does |
|---|---|---|
| D3S | 7:0 |
CLC3SEL3Input select register 1
- Address
0x3C65- Reset
x (not fixed at power-on)- Access
- read/write
- 7D4S7
- 6D4S6
- 5D4S5
- 4D4S4
- 3D4S3
- 2D4S2
- 1D4S1
- 0D4S0
1 field
| Field | Bits | What it does |
|---|---|---|
| D4S | 7:0 |
CLC3GLS0Gate logic select register 0
- Address
0x3C66- Reset
x (not fixed at power-on)- Access
- read/write
- 7G1D4T
- 6G1D4N
- 5G1D3T
- 4G1D3N
- 3G1D2T
- 2G1D2N
- 1G1D1T
- 0G1D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| G1D4T | 7 | |
| G1D4N | 6 | |
| G1D3T | 5 | |
| G1D3N | 4 | |
| G1D2T | 3 | |
| G1D2N | 2 | |
| G1D1T | 1 | |
| G1D1N | 0 |
CLC3GLS1Gate logic select register 1
- Address
0x3C67- Reset
x (not fixed at power-on)- Access
- read/write
- 7G2D4T
- 6G2D4N
- 5G2D3T
- 4G2D3N
- 3G2D2T
- 2G2D2N
- 1G2D1T
- 0G2D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| G2D4T | 7 | |
| G2D4N | 6 | |
| G2D3T | 5 | |
| G2D3N | 4 | |
| G2D2T | 3 | |
| G2D2N | 2 | |
| G2D1T | 1 | |
| G2D1N | 0 |
CLC3GLS2Gate logic select register 2
- Address
0x3C68- Reset
x (not fixed at power-on)- Access
- read/write
- 7G3D4T
- 6G3D4N
- 5G3D3T
- 4G3D3N
- 3G3D2T
- 2G3D2N
- 1G3D1T
- 0G3D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| G3D4T | 7 | |
| G3D4N | 6 | |
| G3D3T | 5 | |
| G3D3N | 4 | |
| G3D2T | 3 | |
| G3D2N | 2 | |
| G3D1T | 1 | |
| G3D1N | 0 |
CLC3GLS3Gate logic select register 3
- Address
0x3C69- Reset
x (not fixed at power-on)- Access
- read/write
- 7G4D4T
- 6G4D4N
- 5G4D3T
- 4G4D3N
- 3G4D2T
- 2G4D2N
- 1G4D1T
- 0G4D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| G4D4T | 7 | |
| G4D4N | 6 | |
| G4D3T | 5 | |
| G4D3N | 4 | |
| G4D2T | 3 | |
| G4D2N | 2 | |
| G4D1T | 1 | |
| G4D1N | 0 |
CLC2CONConfigurable logic cell control
- Address
0x3C6A- Reset
0x00- Access
- read/write
- 7EN
- 6OE
- 5OUT
- 4INTP
- 3INTN
- 2MODE2
- 1MODE1
- 0MODE0
6 fields
| Field | Bits | What it does |
|---|---|---|
| EN | 7 | |
| OE | 6 | |
| OUT | 5 | |
| INTP | 4 | |
| INTN | 3 | |
| MODE | 2:0 |
CLC2POLPolarity control
- Address
0x3C6B- Reset
x (not fixed at power-on)- Access
- read/write
- 7POL
- 6–
- 5–
- 4–
- 3G4POL
- 2G3POL
- 1G2POL
- 0G1POL
5 fields
| Field | Bits | What it does |
|---|---|---|
| POL | 7 | |
| G4POL | 3 | |
| G3POL | 2 | |
| G2POL | 1 | |
| G1POL | 0 |
CLC2SEL0Input select register 1
- Address
0x3C6C- Reset
x (not fixed at power-on)- Access
- read/write
- 7D1S7
- 6D1S6
- 5D1S5
- 4D1S4
- 3D1S3
- 2D1S2
- 1D1S1
- 0D1S0
1 field
| Field | Bits | What it does |
|---|---|---|
| D1S | 7:0 |
CLC2SEL1Input select register 1
- Address
0x3C6D- Reset
x (not fixed at power-on)- Access
- read/write
- 7D2S7
- 6D2S6
- 5D2S5
- 4D2S4
- 3D2S3
- 2D2S2
- 1D2S1
- 0D2S0
1 field
| Field | Bits | What it does |
|---|---|---|
| D2S | 7:0 |
CLC2SEL2Input select register 1
- Address
0x3C6E- Reset
x (not fixed at power-on)- Access
- read/write
- 7D3S7
- 6D3S6
- 5D3S5
- 4D3S4
- 3D3S3
- 2D3S2
- 1D3S1
- 0D3S0
1 field
| Field | Bits | What it does |
|---|---|---|
| D3S | 7:0 |
CLC2SEL3Input select register 1
- Address
0x3C6F- Reset
x (not fixed at power-on)- Access
- read/write
- 7D4S7
- 6D4S6
- 5D4S5
- 4D4S4
- 3D4S3
- 2D4S2
- 1D4S1
- 0D4S0
1 field
| Field | Bits | What it does |
|---|---|---|
| D4S | 7:0 |
CLC2GLS0Gate logic select register 0
- Address
0x3C70- Reset
x (not fixed at power-on)- Access
- read/write
- 7G1D4T
- 6G1D4N
- 5G1D3T
- 4G1D3N
- 3G1D2T
- 2G1D2N
- 1G1D1T
- 0G1D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| G1D4T | 7 | |
| G1D4N | 6 | |
| G1D3T | 5 | |
| G1D3N | 4 | |
| G1D2T | 3 | |
| G1D2N | 2 | |
| G1D1T | 1 | |
| G1D1N | 0 |
CLC2GLS1Gate logic select register 1
- Address
0x3C71- Reset
x (not fixed at power-on)- Access
- read/write
- 7G2D4T
- 6G2D4N
- 5G2D3T
- 4G2D3N
- 3G2D2T
- 2G2D2N
- 1G2D1T
- 0G2D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| G2D4T | 7 | |
| G2D4N | 6 | |
| G2D3T | 5 | |
| G2D3N | 4 | |
| G2D2T | 3 | |
| G2D2N | 2 | |
| G2D1T | 1 | |
| G2D1N | 0 |
CLC2GLS2Gate logic select register 2
- Address
0x3C72- Reset
x (not fixed at power-on)- Access
- read/write
- 7G3D4T
- 6G3D4N
- 5G3D3T
- 4G3D3N
- 3G3D2T
- 2G3D2N
- 1G3D1T
- 0G3D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| G3D4T | 7 | |
| G3D4N | 6 | |
| G3D3T | 5 | |
| G3D3N | 4 | |
| G3D2T | 3 | |
| G3D2N | 2 | |
| G3D1T | 1 | |
| G3D1N | 0 |
CLC2GLS3Gate logic select register 3
- Address
0x3C73- Reset
x (not fixed at power-on)- Access
- read/write
- 7G4D4T
- 6G4D4N
- 5G4D3T
- 4G4D3N
- 3G4D2T
- 2G4D2N
- 1G4D1T
- 0G4D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| G4D4T | 7 | |
| G4D4N | 6 | |
| G4D3T | 5 | |
| G4D3N | 4 | |
| G4D2T | 3 | |
| G4D2N | 2 | |
| G4D1T | 1 | |
| G4D1N | 0 |
CLC1CONConfigurable logic cell control
- Address
0x3C74- Reset
0x00- Access
- read/write
- 7EN
- 6OE
- 5OUT
- 4INTP
- 3INTN
- 2MODE2
- 1MODE1
- 0MODE0
6 fields
| Field | Bits | What it does |
|---|---|---|
| EN | 7 | |
| OE | 6 | |
| OUT | 5 | |
| INTP | 4 | |
| INTN | 3 | |
| MODE | 2:0 |
CLC1POLPolarity control
- Address
0x3C75- Reset
x (not fixed at power-on)- Access
- read/write
- 7POL
- 6–
- 5–
- 4–
- 3G4POL
- 2G3POL
- 1G2POL
- 0G1POL
5 fields
| Field | Bits | What it does |
|---|---|---|
| POL | 7 | |
| G4POL | 3 | |
| G3POL | 2 | |
| G2POL | 1 | |
| G1POL | 0 |
CLC1SEL0Input select register 1
- Address
0x3C76- Reset
x (not fixed at power-on)- Access
- read/write
- 7D1S7
- 6D1S6
- 5D1S5
- 4D1S4
- 3D1S3
- 2D1S2
- 1D1S1
- 0D1S0
1 field
| Field | Bits | What it does |
|---|---|---|
| D1S | 7:0 |
CLC1SEL1Input select register 1
- Address
0x3C77- Reset
x (not fixed at power-on)- Access
- read/write
- 7D2S7
- 6D2S6
- 5D2S5
- 4D2S4
- 3D2S3
- 2D2S2
- 1D2S1
- 0D2S0
1 field
| Field | Bits | What it does |
|---|---|---|
| D2S | 7:0 |
CLC1SEL2Input select register 1
- Address
0x3C78- Reset
x (not fixed at power-on)- Access
- read/write
- 7D3S7
- 6D3S6
- 5D3S5
- 4D3S4
- 3D3S3
- 2D3S2
- 1D3S1
- 0D3S0
1 field
| Field | Bits | What it does |
|---|---|---|
| D3S | 7:0 |
CLC1SEL3Input select register 1
- Address
0x3C79- Reset
x (not fixed at power-on)- Access
- read/write
- 7D4S7
- 6D4S6
- 5D4S5
- 4D4S4
- 3D4S3
- 2D4S2
- 1D4S1
- 0D4S0
1 field
| Field | Bits | What it does |
|---|---|---|
| D4S | 7:0 |
CLC1GLS0Gate logic select register 0
- Address
0x3C7A- Reset
x (not fixed at power-on)- Access
- read/write
- 7G1D4T
- 6G1D4N
- 5G1D3T
- 4G1D3N
- 3G1D2T
- 2G1D2N
- 1G1D1T
- 0G1D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| G1D4T | 7 | |
| G1D4N | 6 | |
| G1D3T | 5 | |
| G1D3N | 4 | |
| G1D2T | 3 | |
| G1D2N | 2 | |
| G1D1T | 1 | |
| G1D1N | 0 |
CLC1GLS1Gate logic select register 1
- Address
0x3C7B- Reset
x (not fixed at power-on)- Access
- read/write
- 7G2D4T
- 6G2D4N
- 5G2D3T
- 4G2D3N
- 3G2D2T
- 2G2D2N
- 1G2D1T
- 0G2D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| G2D4T | 7 | |
| G2D4N | 6 | |
| G2D3T | 5 | |
| G2D3N | 4 | |
| G2D2T | 3 | |
| G2D2N | 2 | |
| G2D1T | 1 | |
| G2D1N | 0 |
CLC1GLS2Gate logic select register 2
- Address
0x3C7C- Reset
x (not fixed at power-on)- Access
- read/write
- 7G3D4T
- 6G3D4N
- 5G3D3T
- 4G3D3N
- 3G3D2T
- 2G3D2N
- 1G3D1T
- 0G3D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| G3D4T | 7 | |
| G3D4N | 6 | |
| G3D3T | 5 | |
| G3D3N | 4 | |
| G3D2T | 3 | |
| G3D2N | 2 | |
| G3D1T | 1 | |
| G3D1N | 0 |
CLC1GLS3Gate logic select register 3
- Address
0x3C7D- Reset
x (not fixed at power-on)- Access
- read/write
- 7G4D4T
- 6G4D4N
- 5G4D3T
- 4G4D3N
- 3G4D2T
- 2G4D2N
- 1G4D1T
- 0G4D1N
8 fields
| Field | Bits | What it does |
|---|---|---|
| G4D4T | 7 | |
| G4D4N | 6 | |
| G4D3T | 5 | |
| G4D3N | 4 | |
| G4D2T | 3 | |
| G4D2N | 2 | |
| G4D1T | 1 | |
| G4D1N | 0 |
CLCDATA0
- Address
0x3C7E- Reset
0x00- Access
- read only
- 7–
- 6–
- 5–
- 4–
- 3CLC4OUT
- 2CLC3OUT
- 1CLC2OUT
- 0CLC1OUT
4 fields
| Field | Bits | What it does |
|---|---|---|
| CLC4OUT | 3 | |
| CLC3OUT | 2 | |
| CLC2OUT | 1 | |
| CLC1OUT | 0 |