PIC18LF56K42 PORTS registers The 19 registers of PORTS (I/O port control), from 0x3A48, with their reset value and every field. The PIC18LF56K42 has 663 registers in 55 peripherals, one page each.
PORTS I/O port control CCDPA
Address 0x3A48
Reset 0x00
Access read/write 7 CCDPA7 6 CCDPA6 5 CCDPA5 4 CCDPA4 3 CCDPA3 2 CCDPA2 1 CCDPA1 0 CCDPA0 8 fields
Field Bits What it does CCDPA7 7 CCDPA6 6 CCDPA5 5 CCDPA4 4 CCDPA3 3 CCDPA2 2 CCDPA1 1 CCDPA0 0
CCDNA
Address 0x3A49
Reset 0x00
Access read/write 7 CCDNA7 6 CCDNA6 5 CCDNA5 4 CCDNA4 3 CCDNA3 2 CCDNA2 1 CCDNA1 0 CCDNA0 8 fields
Field Bits What it does CCDNA7 7 CCDNA6 6 CCDNA5 5 CCDNA4 4 CCDNA3 3 CCDNA2 2 CCDNA1 1 CCDNA0 0
CCDPB
Address 0x3A58
Reset 0x00
Access read/write 7 CCDPB7 6 CCDPB6 5 CCDPB5 4 CCDPB4 3 CCDPB3 2 CCDPB2 1 CCDPB1 0 CCDPB0 8 fields
Field Bits What it does CCDPB7 7 CCDPB6 6 CCDPB5 5 CCDPB4 4 CCDPB3 3 CCDPB2 2 CCDPB1 1 CCDPB0 0
CCDNB
Address 0x3A59
Reset 0x00
Access read/write 7 CCDNB7 6 CCDNB6 5 CCDNB5 4 CCDNB4 3 CCDNB3 2 CCDNB2 1 CCDNB1 0 CCDNB0 8 fields
Field Bits What it does CCDNB7 7 CCDNB6 6 CCDNB5 5 CCDNB4 4 CCDNB3 3 CCDNB2 2 CCDNB1 1 CCDNB0 0
RB1I2C
Address 0x3A5A
Reset 0x00
Access read/write 7 – 6 SLEW 5 PU1 4 PU0 3 – 2 – 1 TH1 0 TH0 3 fields
Field Bits What it does SLEW 6 PU 5:4 TH 1:0
RB2I2C
Address 0x3A5B
Reset 0x00
Access read/write 7 – 6 SLEW 5 PU1 4 PU0 3 – 2 – 1 TH1 0 TH0 3 fields
Field Bits What it does SLEW 6 PU 5:4 TH 1:0
CCDPC
Address 0x3A68
Reset 0x00
Access read/write 7 CCDPC7 6 CCDPC6 5 CCDPC5 4 CCDPC4 3 CCDPC3 2 CCDPC2 1 CCDPC1 0 CCDPC0 8 fields
Field Bits What it does CCDPC7 7 CCDPC6 6 CCDPC5 5 CCDPC4 4 CCDPC3 3 CCDPC2 2 CCDPC1 1 CCDPC0 0
CCDNC
Address 0x3A69
Reset 0x00
Access read/write 7 CCDNC7 6 CCDNC6 5 CCDNC5 4 CCDNC4 3 CCDNC3 2 CCDNC2 1 CCDNC1 0 CCDNC0 8 fields
Field Bits What it does CCDNC7 7 CCDNC6 6 CCDNC5 5 CCDNC4 4 CCDNC3 3 CCDNC2 2 CCDNC1 1 CCDNC0 0
RC3I2C
Address 0x3A6A
Reset 0x00
Access read/write 7 – 6 SLEW 5 PU1 4 PU0 3 – 2 – 1 TH1 0 TH0 3 fields
Field Bits What it does SLEW 6 PU 5:4 TH 1:0
RC4I2C
Address 0x3A6B
Reset 0x00
Access read/write 7 – 6 SLEW 5 PU1 4 PU0 3 – 2 – 1 TH1 0 TH0 3 fields
Field Bits What it does SLEW 6 PU 5:4 TH 1:0
CCDPD
Address 0x3A78
Reset 0x00
Access read/write 7 CCDPD7 6 CCDPD6 5 CCDPD5 4 CCDPD4 3 CCDPD3 2 CCDPD2 1 CCDPD1 0 CCDPD0 8 fields
Field Bits What it does CCDPD7 7 CCDPD6 6 CCDPD5 5 CCDPD4 4 CCDPD3 3 CCDPD2 2 CCDPD1 1 CCDPD0 0
CCDND
Address 0x3A79
Reset 0x00
Access read/write 7 CCDND7 6 CCDND6 5 CCDND5 4 CCDND4 3 CCDND3 2 CCDND2 1 CCDND1 0 CCDND0 8 fields
Field Bits What it does CCDND7 7 CCDND6 6 CCDND5 5 CCDND4 4 CCDND3 3 CCDND2 2 CCDND1 1 CCDND0 0
RD0I2C
Address 0x3A7A
Reset 0x00
Access read/write 7 – 6 SLEW 5 PU1 4 PU0 3 – 2 – 1 TH1 0 TH0 3 fields
Field Bits What it does SLEW 6 PU 5:4 TH 1:0
RD1I2C
Address 0x3A7B
Reset 0x00
Access read/write 7 – 6 SLEW 5 PU1 4 PU0 3 – 2 – 1 TH1 0 TH0 3 fields
Field Bits What it does SLEW 6 PU 5:4 TH 1:0
CCDPE
Address 0x3A88
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 CCDPE2 1 CCDPE1 0 CCDPE0 3 fields
Field Bits What it does CCDPE2 2 CCDPE1 1 CCDPE0 0
CCDNE
Address 0x3A89
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 CCDNE2 1 CCDNE1 0 CCDNE0 3 fields
Field Bits What it does CCDNE2 2 CCDNE1 1 CCDNE0 0
CCDPF
Address 0x3A98
Reset 0x00
Access read/write 7 CCDPF7 6 CCDPF6 5 CCDPF5 4 CCDPF4 3 CCDPF3 2 CCDPF2 1 CCDPF1 0 CCDPF0 8 fields
Field Bits What it does CCDPF7 7 CCDPF6 6 CCDPF5 5 CCDPF4 4 CCDPF3 3 CCDPF2 2 CCDPF1 1 CCDPF0 0
CCDNF
Address 0x3A99
Reset 0x00
Access read/write 7 CCDNF7 6 CCDNF6 5 CCDNF5 4 CCDNF4 3 CCDNF3 2 CCDNF2 1 CCDNF1 0 CCDNF0 8 fields
Field Bits What it does CCDNF7 7 CCDNF6 6 CCDNF5 5 CCDNF4 4 CCDNF3 3 CCDNF2 2 CCDNF1 1 CCDNF0 0
7 EN 6 – 5 – 4 – 3 – 2 – 1 DS1 0 DS0 2 fields
Field Bits What it does EN 7 DS 1:0
BETA