SSP1CLKPPS
- Address
0xE19- Reset
0x13- Access
- read/write
- 7PORT1
- 6PORT0
- 5–
- 4–
- 3–
- 2PIN2
- 1PIN1
- 0PIN0
2 fields
| Field | Bits | What it does |
|---|---|---|
| PORT | 7:6 | |
| PIN | 2:0 |
The 20 registers of MSSP (Master synchronous serial port (SPI, I²C)), from 0xE19, with their reset value and every field. The PIC18LF67K40 has 523 registers in 49 peripherals, one page each.
0xE190x13| Field | Bits | What it does |
|---|---|---|
| PORT | 7:6 | |
| PIN | 2:0 |
0xE1A0x14| Field | Bits | What it does |
|---|---|---|
| PORT | 7:6 | |
| PIN | 2:0 |
0xE1B0x2F| Field | Bits | What it does |
|---|---|---|
| PORT | 8:6 | |
| PIN | 2:0 |
0xE1C0x1E| Field | Bits | What it does |
|---|---|---|
| PORT | 7:6 | |
| PIN | 2:0 |
0xE1D0x1D| Field | Bits | What it does |
|---|---|---|
| PORT | 7:6 | |
| PIN | 2:0 |
0xE1E0x1F| Field | Bits | What it does |
|---|---|---|
| PORT | 7:6 | |
| PIN | 2:0 |
0xED5x (not fixed at power-on)| Field | Bits | What it does |
|---|---|---|
| SSPBUF | 7:0 |
0xED60x00| Field | Bits | What it does |
|---|---|---|
| SSPADD | 7:0 |
0xED70xFF| Field | Bits | What it does |
|---|---|---|
| SSPMSK | 7:0 |
0xED80x00| Field | Bits | What it does |
|---|---|---|
| SMP | 7 | SPI Data Input Sample Phase bit |
| CKE | 6 | SPI Clock Edge Select bit |
| D_nA | 5 | Data/Address bit |
| P | 4 | Stop bit |
| S | 3 | Start bit |
| R_nW | 2 | Read/Write Information bit |
| UA | 1 | Update Address bit |
| BF | 0 | Buffer Full Status bit (Receive mode only) |
0xED90x00| Field | Bits | What it does |
|---|---|---|
| WCOL | 7 | Write Collision Detect bit (Transmit mode only) |
| SSPOV | 6 | Receive Overflow Indicator bit |
| SSPEN | 5 | Synchronous Serial Port Enable bit |
| CKP | 4 | Clock Polarity Select bit |
| SSPM | 3:0 | Synchronous Serial Port Mode Select bits |
0xEDA0x00| Field | Bits | What it does |
|---|---|---|
| GCEN | 7 | General Call Enable bit (Slave mode only) |
| ACKSTAT | 6 | Acknowledge Status bit (Transmission only) |
| ACKDT | 5 | Acknowledge Data bit (Receive mode only) |
| ACKEN | 4 | Acknowledge Sequence Enable bit (Master Receive mode only) |
| RCEN | 3 | Receive Enable bit (Master mode only) |
| PEN | 2 | Stop Condition Enable bit (Master mode only) |
| RSEN | 1 | Repeated Start Condition Enable bit (Master mode only) |
| SEN | 0 | Start Condition Enable/Stretch Enable bit |
0xEDB0x00| Field | Bits | What it does |
|---|---|---|
| ACKTIM | 7 | |
| PCIE | 6 | |
| SCIE | 5 | |
| BOEN | 4 | |
| SDAHT | 3 | |
| SBCDE | 2 | |
| AHEN | 1 | |
| DHEN | 0 |
0xF91x (not fixed at power-on)| Field | Bits | What it does |
|---|---|---|
| SSPBUF | 7:0 |
0xF920x00| Field | Bits | What it does |
|---|---|---|
| SSPADD | 7:0 |
0xF930xFF| Field | Bits | What it does |
|---|---|---|
| SSPMSK | 7:0 |
0xF940x00| Field | Bits | What it does |
|---|---|---|
| SMP | 7 | SPI Data Input Sample Phase bit |
| CKE | 6 | SPI Clock Edge Select bit |
| D_nA | 5 | Data/Address bit |
| P | 4 | Stop bit |
| S | 3 | Start bit |
| R_nW | 2 | Read/Write Information bit |
| UA | 1 | Update Address bit |
| BF | 0 | Buffer Full Status bit (Receive mode only) |
0xF950x00| Field | Bits | What it does |
|---|---|---|
| WCOL | 7 | Write Collision Detect bit (Transmit mode only) |
| SSPOV | 6 | Receive Overflow Indicator bit |
| SSPEN | 5 | Synchronous Serial Port Enable bit |
| CKP | 4 | Clock Polarity Select bit |
| SSPM | 3:0 | Synchronous Serial Port Mode Select bits |
0xF960x00| Field | Bits | What it does |
|---|---|---|
| GCEN | 7 | General Call Enable bit (Slave mode only) |
| ACKSTAT | 6 | Acknowledge Status bit (Transmission only) |
| ACKDT | 5 | Acknowledge Data bit (Receive mode only) |
| ACKEN | 4 | Acknowledge Sequence Enable bit (Master Receive mode only) |
| RCEN | 3 | Receive Enable bit (Master mode only) |
| PEN | 2 | Stop Condition Enable bit (Master mode only) |
| RSEN | 1 | Repeated Start Condition Enable bit (Master mode only) |
| SEN | 0 | Start Condition Enable/Stretch Enable bit |
0xF970x00| Field | Bits | What it does |
|---|---|---|
| ACKTIM | 7 | |
| PCIE | 6 | |
| SCIE | 5 | |
| BOEN | 4 | |
| SDAHT | 3 | |
| SBCDE | 2 | |
| AHEN | 1 | |
| DHEN | 0 |