PIC32CK1012GC00064 HMATRIX registers

The 89 registers of HMATRIX (HSB Matrix), from 0x44806000, with their reset value and every field. The PIC32CK1012GC00064 has 5094 registers in 60 peripherals, one page each.

HMATRIX HSB Matrix

MCFG0Master Configuration

Address: 0x44806000
Reset: 0x00000002
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ULBT	2:0	Undefined Length Burst Type `0` Infinite Length `1` Single Access `2` Four Beat Burst `3` Eight Beat Burst `4` Sixteen Beat Burst

MCFG1Master Configuration

Address: 0x44806004
Reset: 0x00000002
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ULBT	2:0	Undefined Length Burst Type `0` Infinite Length `1` Single Access `2` Four Beat Burst `3` Eight Beat Burst `4` Sixteen Beat Burst

MCFG2Master Configuration

Address: 0x44806008
Reset: 0x00000002
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ULBT	2:0	Undefined Length Burst Type `0` Infinite Length `1` Single Access `2` Four Beat Burst `3` Eight Beat Burst `4` Sixteen Beat Burst

MCFG3Master Configuration

Address: 0x4480600C
Reset: 0x00000002
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ULBT	2:0	Undefined Length Burst Type `0` Infinite Length `1` Single Access `2` Four Beat Burst `3` Eight Beat Burst `4` Sixteen Beat Burst

MCFG4Master Configuration

Address: 0x44806010
Reset: 0x00000002
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ULBT	2:0	Undefined Length Burst Type `0` Infinite Length `1` Single Access `2` Four Beat Burst `3` Eight Beat Burst `4` Sixteen Beat Burst

MCFG5Master Configuration

Address: 0x44806014
Reset: 0x00000002
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ULBT	2:0	Undefined Length Burst Type `0` Infinite Length `1` Single Access `2` Four Beat Burst `3` Eight Beat Burst `4` Sixteen Beat Burst

MCFG6Master Configuration

Address: 0x44806018
Reset: 0x00000002
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ULBT	2:0	Undefined Length Burst Type `0` Infinite Length `1` Single Access `2` Four Beat Burst `3` Eight Beat Burst `4` Sixteen Beat Burst

MCFG7Master Configuration

Address: 0x4480601C
Reset: 0x00000002
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ULBT	2:0	Undefined Length Burst Type `0` Infinite Length `1` Single Access `2` Four Beat Burst `3` Eight Beat Burst `4` Sixteen Beat Burst

MCFG8Master Configuration

Address: 0x44806020
Reset: 0x00000002
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ULBT	2:0	Undefined Length Burst Type `0` Infinite Length `1` Single Access `2` Four Beat Burst `3` Eight Beat Burst `4` Sixteen Beat Burst

MCFG9Master Configuration

Address: 0x44806024
Reset: 0x00000002
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ULBT	2:0	Undefined Length Burst Type `0` Infinite Length `1` Single Access `2` Four Beat Burst `3` Eight Beat Burst `4` Sixteen Beat Burst

MCFG10Master Configuration

Address: 0x44806028
Reset: 0x00000002
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ULBT	2:0	Undefined Length Burst Type `0` Infinite Length `1` Single Access `2` Four Beat Burst `3` Eight Beat Burst `4` Sixteen Beat Burst

MCFG11Master Configuration

Address: 0x4480602C
Reset: 0x00000002
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ULBT	2:0	Undefined Length Burst Type `0` Infinite Length `1` Single Access `2` Four Beat Burst `3` Eight Beat Burst `4` Sixteen Beat Burst

MCFG12Master Configuration

Address: 0x44806030
Reset: 0x00000002
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ULBT	2:0	Undefined Length Burst Type `0` Infinite Length `1` Single Access `2` Four Beat Burst `3` Eight Beat Burst `4` Sixteen Beat Burst

MCFG13Master Configuration

Address: 0x44806034
Reset: 0x00000002
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ULBT	2:0	Undefined Length Burst Type `0` Infinite Length `1` Single Access `2` Four Beat Burst `3` Eight Beat Burst `4` Sixteen Beat Burst

MCFG14Master Configuration

Address: 0x44806038
Reset: 0x00000002
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ULBT	2:0	Undefined Length Burst Type `0` Infinite Length `1` Single Access `2` Four Beat Burst `3` Eight Beat Burst `4` Sixteen Beat Burst

MCFG15Master Configuration

Address: 0x4480603C
Reset: 0x00000002
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ULBT	2:0	Undefined Length Burst Type `0` Infinite Length `1` Single Access `2` Four Beat Burst `3` Eight Beat Burst `4` Sixteen Beat Burst

SCFG0Slave Configuration

Address: 0x44806040
Reset: 0x00000010
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
FIXED_DEFMSTR	21:18	Fixed Index of Default Master
DEFMSTR_TYPE	17:16	Default Master Type `0` No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. `1` Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. `2` Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE	8:0	Maximum Number of Allowed Cycles for a Burst

SCFG1Slave Configuration

Address: 0x44806044
Reset: 0x00000010
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
FIXED_DEFMSTR	21:18	Fixed Index of Default Master
DEFMSTR_TYPE	17:16	Default Master Type `0` No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. `1` Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. `2` Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE	8:0	Maximum Number of Allowed Cycles for a Burst

SCFG2Slave Configuration

Address: 0x44806048
Reset: 0x00000010
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
FIXED_DEFMSTR	21:18	Fixed Index of Default Master
DEFMSTR_TYPE	17:16	Default Master Type `0` No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. `1` Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. `2` Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE	8:0	Maximum Number of Allowed Cycles for a Burst

SCFG3Slave Configuration

Address: 0x4480604C
Reset: 0x00000010
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
FIXED_DEFMSTR	21:18	Fixed Index of Default Master
DEFMSTR_TYPE	17:16	Default Master Type `0` No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. `1` Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. `2` Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE	8:0	Maximum Number of Allowed Cycles for a Burst

SCFG4Slave Configuration

Address: 0x44806050
Reset: 0x00000010
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
FIXED_DEFMSTR	21:18	Fixed Index of Default Master
DEFMSTR_TYPE	17:16	Default Master Type `0` No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. `1` Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. `2` Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE	8:0	Maximum Number of Allowed Cycles for a Burst

SCFG5Slave Configuration

Address: 0x44806054
Reset: 0x00000010
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
FIXED_DEFMSTR	21:18	Fixed Index of Default Master
DEFMSTR_TYPE	17:16	Default Master Type `0` No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. `1` Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. `2` Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE	8:0	Maximum Number of Allowed Cycles for a Burst

SCFG6Slave Configuration

Address: 0x44806058
Reset: 0x00000010
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
FIXED_DEFMSTR	21:18	Fixed Index of Default Master
DEFMSTR_TYPE	17:16	Default Master Type `0` No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. `1` Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. `2` Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE	8:0	Maximum Number of Allowed Cycles for a Burst

SCFG7Slave Configuration

Address: 0x4480605C
Reset: 0x00000010
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
FIXED_DEFMSTR	21:18	Fixed Index of Default Master
DEFMSTR_TYPE	17:16	Default Master Type `0` No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. `1` Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. `2` Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE	8:0	Maximum Number of Allowed Cycles for a Burst

SCFG8Slave Configuration

Address: 0x44806060
Reset: 0x00000010
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
FIXED_DEFMSTR	21:18	Fixed Index of Default Master
DEFMSTR_TYPE	17:16	Default Master Type `0` No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. `1` Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. `2` Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE	8:0	Maximum Number of Allowed Cycles for a Burst

SCFG9Slave Configuration

Address: 0x44806064
Reset: 0x00000010
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
FIXED_DEFMSTR	21:18	Fixed Index of Default Master
DEFMSTR_TYPE	17:16	Default Master Type `0` No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. `1` Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. `2` Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE	8:0	Maximum Number of Allowed Cycles for a Burst

SCFG10Slave Configuration

Address: 0x44806068
Reset: 0x00000010
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
FIXED_DEFMSTR	21:18	Fixed Index of Default Master
DEFMSTR_TYPE	17:16	Default Master Type `0` No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. `1` Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. `2` Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE	8:0	Maximum Number of Allowed Cycles for a Burst

SCFG11Slave Configuration

Address: 0x4480606C
Reset: 0x00000010
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
FIXED_DEFMSTR	21:18	Fixed Index of Default Master
DEFMSTR_TYPE	17:16	Default Master Type `0` No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. `1` Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. `2` Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE	8:0	Maximum Number of Allowed Cycles for a Burst

SCFG12Slave Configuration

Address: 0x44806070
Reset: 0x00000010
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
FIXED_DEFMSTR	21:18	Fixed Index of Default Master
DEFMSTR_TYPE	17:16	Default Master Type `0` No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst. `1` Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave. `2` Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE	8:0	Maximum Number of Allowed Cycles for a Burst

PRS0.PRASPriority A for Slave

Address: 0x44806080
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN7	30	Latency Quality Of Service Enable for Master 7
M7PR	29:28	Master 7 Priority
LQOSEN6	26	Latency Quality Of Service Enable for Master 6
M6PR	25:24	Master 6 Priority
LQOSEN5	22	Latency Quality Of Service Enable for Master 5
M5PR	21:20	Master 5 Priority
LQOSEN4	18	Latency Quality Of Service Enable for Master 4
M4PR	17:16	Master 4 Priority
LQOSEN3	14	Latency Quality Of Service Enable for Master 3
M3PR	13:12	Master 3 Priority
LQOSEN2	10	Latency Quality Of Service Enable for Master 2
M2PR	9:8	Master 2 Priority
LQOSEN1	6	Latency Quality Of Service Enable for Master 1
M1PR	5:4	Master 1 Priority
LQOSEN0	2	Latency Quality Of Service Enable for Master 0
M0PR	1:0	Master 0 Priority

PRS0.PRBSPriority B for Slave

Address: 0x44806084
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN15	30	Latency Quality Of Service Enable for Master 15
M15PR	29:28	Master 15 Priority
LQOSEN14	26	Latency Quality Of Service Enable for Master 14
M14PR	25:24	Master 14 Priority
LQOSEN13	22	Latency Quality Of Service Enable for Master 13
M13PR	21:20	Master 13 Priority
LQOSEN12	18	Latency Quality Of Service Enable for Master 12
M12PR	17:16	Master 12 Priority
LQOSEN11	14	Latency Quality Of Service Enable for Master 11
M11PR	13:12	Master 11 Priority
LQOSEN10	10	Latency Quality Of Service Enable for Master 10
M10PR	9:8	Master 10 Priority
LQOSEN9	6	Latency Quality Of Service Enable for Master 9
M9PR	5:4	Master 9 Priority
LQOSEN8	2	Latency Quality Of Service Enable for Master 8
M8PR	1:0	Master 8 Priority

PRS1.PRASPriority A for Slave

Address: 0x44806088
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN7	30	Latency Quality Of Service Enable for Master 7
M7PR	29:28	Master 7 Priority
LQOSEN6	26	Latency Quality Of Service Enable for Master 6
M6PR	25:24	Master 6 Priority
LQOSEN5	22	Latency Quality Of Service Enable for Master 5
M5PR	21:20	Master 5 Priority
LQOSEN4	18	Latency Quality Of Service Enable for Master 4
M4PR	17:16	Master 4 Priority
LQOSEN3	14	Latency Quality Of Service Enable for Master 3
M3PR	13:12	Master 3 Priority
LQOSEN2	10	Latency Quality Of Service Enable for Master 2
M2PR	9:8	Master 2 Priority
LQOSEN1	6	Latency Quality Of Service Enable for Master 1
M1PR	5:4	Master 1 Priority
LQOSEN0	2	Latency Quality Of Service Enable for Master 0
M0PR	1:0	Master 0 Priority

PRS1.PRBSPriority B for Slave

Address: 0x4480608C
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN15	30	Latency Quality Of Service Enable for Master 15
M15PR	29:28	Master 15 Priority
LQOSEN14	26	Latency Quality Of Service Enable for Master 14
M14PR	25:24	Master 14 Priority
LQOSEN13	22	Latency Quality Of Service Enable for Master 13
M13PR	21:20	Master 13 Priority
LQOSEN12	18	Latency Quality Of Service Enable for Master 12
M12PR	17:16	Master 12 Priority
LQOSEN11	14	Latency Quality Of Service Enable for Master 11
M11PR	13:12	Master 11 Priority
LQOSEN10	10	Latency Quality Of Service Enable for Master 10
M10PR	9:8	Master 10 Priority
LQOSEN9	6	Latency Quality Of Service Enable for Master 9
M9PR	5:4	Master 9 Priority
LQOSEN8	2	Latency Quality Of Service Enable for Master 8
M8PR	1:0	Master 8 Priority

PRS2.PRASPriority A for Slave

Address: 0x44806090
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN7	30	Latency Quality Of Service Enable for Master 7
M7PR	29:28	Master 7 Priority
LQOSEN6	26	Latency Quality Of Service Enable for Master 6
M6PR	25:24	Master 6 Priority
LQOSEN5	22	Latency Quality Of Service Enable for Master 5
M5PR	21:20	Master 5 Priority
LQOSEN4	18	Latency Quality Of Service Enable for Master 4
M4PR	17:16	Master 4 Priority
LQOSEN3	14	Latency Quality Of Service Enable for Master 3
M3PR	13:12	Master 3 Priority
LQOSEN2	10	Latency Quality Of Service Enable for Master 2
M2PR	9:8	Master 2 Priority
LQOSEN1	6	Latency Quality Of Service Enable for Master 1
M1PR	5:4	Master 1 Priority
LQOSEN0	2	Latency Quality Of Service Enable for Master 0
M0PR	1:0	Master 0 Priority

PRS2.PRBSPriority B for Slave

Address: 0x44806094
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN15	30	Latency Quality Of Service Enable for Master 15
M15PR	29:28	Master 15 Priority
LQOSEN14	26	Latency Quality Of Service Enable for Master 14
M14PR	25:24	Master 14 Priority
LQOSEN13	22	Latency Quality Of Service Enable for Master 13
M13PR	21:20	Master 13 Priority
LQOSEN12	18	Latency Quality Of Service Enable for Master 12
M12PR	17:16	Master 12 Priority
LQOSEN11	14	Latency Quality Of Service Enable for Master 11
M11PR	13:12	Master 11 Priority
LQOSEN10	10	Latency Quality Of Service Enable for Master 10
M10PR	9:8	Master 10 Priority
LQOSEN9	6	Latency Quality Of Service Enable for Master 9
M9PR	5:4	Master 9 Priority
LQOSEN8	2	Latency Quality Of Service Enable for Master 8
M8PR	1:0	Master 8 Priority

PRS3.PRASPriority A for Slave

Address: 0x44806098
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN7	30	Latency Quality Of Service Enable for Master 7
M7PR	29:28	Master 7 Priority
LQOSEN6	26	Latency Quality Of Service Enable for Master 6
M6PR	25:24	Master 6 Priority
LQOSEN5	22	Latency Quality Of Service Enable for Master 5
M5PR	21:20	Master 5 Priority
LQOSEN4	18	Latency Quality Of Service Enable for Master 4
M4PR	17:16	Master 4 Priority
LQOSEN3	14	Latency Quality Of Service Enable for Master 3
M3PR	13:12	Master 3 Priority
LQOSEN2	10	Latency Quality Of Service Enable for Master 2
M2PR	9:8	Master 2 Priority
LQOSEN1	6	Latency Quality Of Service Enable for Master 1
M1PR	5:4	Master 1 Priority
LQOSEN0	2	Latency Quality Of Service Enable for Master 0
M0PR	1:0	Master 0 Priority

PRS3.PRBSPriority B for Slave

Address: 0x4480609C
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN15	30	Latency Quality Of Service Enable for Master 15
M15PR	29:28	Master 15 Priority
LQOSEN14	26	Latency Quality Of Service Enable for Master 14
M14PR	25:24	Master 14 Priority
LQOSEN13	22	Latency Quality Of Service Enable for Master 13
M13PR	21:20	Master 13 Priority
LQOSEN12	18	Latency Quality Of Service Enable for Master 12
M12PR	17:16	Master 12 Priority
LQOSEN11	14	Latency Quality Of Service Enable for Master 11
M11PR	13:12	Master 11 Priority
LQOSEN10	10	Latency Quality Of Service Enable for Master 10
M10PR	9:8	Master 10 Priority
LQOSEN9	6	Latency Quality Of Service Enable for Master 9
M9PR	5:4	Master 9 Priority
LQOSEN8	2	Latency Quality Of Service Enable for Master 8
M8PR	1:0	Master 8 Priority

PRS4.PRASPriority A for Slave

Address: 0x448060A0
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN7	30	Latency Quality Of Service Enable for Master 7
M7PR	29:28	Master 7 Priority
LQOSEN6	26	Latency Quality Of Service Enable for Master 6
M6PR	25:24	Master 6 Priority
LQOSEN5	22	Latency Quality Of Service Enable for Master 5
M5PR	21:20	Master 5 Priority
LQOSEN4	18	Latency Quality Of Service Enable for Master 4
M4PR	17:16	Master 4 Priority
LQOSEN3	14	Latency Quality Of Service Enable for Master 3
M3PR	13:12	Master 3 Priority
LQOSEN2	10	Latency Quality Of Service Enable for Master 2
M2PR	9:8	Master 2 Priority
LQOSEN1	6	Latency Quality Of Service Enable for Master 1
M1PR	5:4	Master 1 Priority
LQOSEN0	2	Latency Quality Of Service Enable for Master 0
M0PR	1:0	Master 0 Priority

PRS4.PRBSPriority B for Slave

Address: 0x448060A4
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN15	30	Latency Quality Of Service Enable for Master 15
M15PR	29:28	Master 15 Priority
LQOSEN14	26	Latency Quality Of Service Enable for Master 14
M14PR	25:24	Master 14 Priority
LQOSEN13	22	Latency Quality Of Service Enable for Master 13
M13PR	21:20	Master 13 Priority
LQOSEN12	18	Latency Quality Of Service Enable for Master 12
M12PR	17:16	Master 12 Priority
LQOSEN11	14	Latency Quality Of Service Enable for Master 11
M11PR	13:12	Master 11 Priority
LQOSEN10	10	Latency Quality Of Service Enable for Master 10
M10PR	9:8	Master 10 Priority
LQOSEN9	6	Latency Quality Of Service Enable for Master 9
M9PR	5:4	Master 9 Priority
LQOSEN8	2	Latency Quality Of Service Enable for Master 8
M8PR	1:0	Master 8 Priority

PRS5.PRASPriority A for Slave

Address: 0x448060A8
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN7	30	Latency Quality Of Service Enable for Master 7
M7PR	29:28	Master 7 Priority
LQOSEN6	26	Latency Quality Of Service Enable for Master 6
M6PR	25:24	Master 6 Priority
LQOSEN5	22	Latency Quality Of Service Enable for Master 5
M5PR	21:20	Master 5 Priority
LQOSEN4	18	Latency Quality Of Service Enable for Master 4
M4PR	17:16	Master 4 Priority
LQOSEN3	14	Latency Quality Of Service Enable for Master 3
M3PR	13:12	Master 3 Priority
LQOSEN2	10	Latency Quality Of Service Enable for Master 2
M2PR	9:8	Master 2 Priority
LQOSEN1	6	Latency Quality Of Service Enable for Master 1
M1PR	5:4	Master 1 Priority
LQOSEN0	2	Latency Quality Of Service Enable for Master 0
M0PR	1:0	Master 0 Priority

PRS5.PRBSPriority B for Slave

Address: 0x448060AC
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN15	30	Latency Quality Of Service Enable for Master 15
M15PR	29:28	Master 15 Priority
LQOSEN14	26	Latency Quality Of Service Enable for Master 14
M14PR	25:24	Master 14 Priority
LQOSEN13	22	Latency Quality Of Service Enable for Master 13
M13PR	21:20	Master 13 Priority
LQOSEN12	18	Latency Quality Of Service Enable for Master 12
M12PR	17:16	Master 12 Priority
LQOSEN11	14	Latency Quality Of Service Enable for Master 11
M11PR	13:12	Master 11 Priority
LQOSEN10	10	Latency Quality Of Service Enable for Master 10
M10PR	9:8	Master 10 Priority
LQOSEN9	6	Latency Quality Of Service Enable for Master 9
M9PR	5:4	Master 9 Priority
LQOSEN8	2	Latency Quality Of Service Enable for Master 8
M8PR	1:0	Master 8 Priority

PRS6.PRASPriority A for Slave

Address: 0x448060B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN7	30	Latency Quality Of Service Enable for Master 7
M7PR	29:28	Master 7 Priority
LQOSEN6	26	Latency Quality Of Service Enable for Master 6
M6PR	25:24	Master 6 Priority
LQOSEN5	22	Latency Quality Of Service Enable for Master 5
M5PR	21:20	Master 5 Priority
LQOSEN4	18	Latency Quality Of Service Enable for Master 4
M4PR	17:16	Master 4 Priority
LQOSEN3	14	Latency Quality Of Service Enable for Master 3
M3PR	13:12	Master 3 Priority
LQOSEN2	10	Latency Quality Of Service Enable for Master 2
M2PR	9:8	Master 2 Priority
LQOSEN1	6	Latency Quality Of Service Enable for Master 1
M1PR	5:4	Master 1 Priority
LQOSEN0	2	Latency Quality Of Service Enable for Master 0
M0PR	1:0	Master 0 Priority

PRS6.PRBSPriority B for Slave

Address: 0x448060B4
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN15	30	Latency Quality Of Service Enable for Master 15
M15PR	29:28	Master 15 Priority
LQOSEN14	26	Latency Quality Of Service Enable for Master 14
M14PR	25:24	Master 14 Priority
LQOSEN13	22	Latency Quality Of Service Enable for Master 13
M13PR	21:20	Master 13 Priority
LQOSEN12	18	Latency Quality Of Service Enable for Master 12
M12PR	17:16	Master 12 Priority
LQOSEN11	14	Latency Quality Of Service Enable for Master 11
M11PR	13:12	Master 11 Priority
LQOSEN10	10	Latency Quality Of Service Enable for Master 10
M10PR	9:8	Master 10 Priority
LQOSEN9	6	Latency Quality Of Service Enable for Master 9
M9PR	5:4	Master 9 Priority
LQOSEN8	2	Latency Quality Of Service Enable for Master 8
M8PR	1:0	Master 8 Priority

PRS7.PRASPriority A for Slave

Address: 0x448060B8
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN7	30	Latency Quality Of Service Enable for Master 7
M7PR	29:28	Master 7 Priority
LQOSEN6	26	Latency Quality Of Service Enable for Master 6
M6PR	25:24	Master 6 Priority
LQOSEN5	22	Latency Quality Of Service Enable for Master 5
M5PR	21:20	Master 5 Priority
LQOSEN4	18	Latency Quality Of Service Enable for Master 4
M4PR	17:16	Master 4 Priority
LQOSEN3	14	Latency Quality Of Service Enable for Master 3
M3PR	13:12	Master 3 Priority
LQOSEN2	10	Latency Quality Of Service Enable for Master 2
M2PR	9:8	Master 2 Priority
LQOSEN1	6	Latency Quality Of Service Enable for Master 1
M1PR	5:4	Master 1 Priority
LQOSEN0	2	Latency Quality Of Service Enable for Master 0
M0PR	1:0	Master 0 Priority

PRS7.PRBSPriority B for Slave

Address: 0x448060BC
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN15	30	Latency Quality Of Service Enable for Master 15
M15PR	29:28	Master 15 Priority
LQOSEN14	26	Latency Quality Of Service Enable for Master 14
M14PR	25:24	Master 14 Priority
LQOSEN13	22	Latency Quality Of Service Enable for Master 13
M13PR	21:20	Master 13 Priority
LQOSEN12	18	Latency Quality Of Service Enable for Master 12
M12PR	17:16	Master 12 Priority
LQOSEN11	14	Latency Quality Of Service Enable for Master 11
M11PR	13:12	Master 11 Priority
LQOSEN10	10	Latency Quality Of Service Enable for Master 10
M10PR	9:8	Master 10 Priority
LQOSEN9	6	Latency Quality Of Service Enable for Master 9
M9PR	5:4	Master 9 Priority
LQOSEN8	2	Latency Quality Of Service Enable for Master 8
M8PR	1:0	Master 8 Priority

PRS8.PRASPriority A for Slave

Address: 0x448060C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN7	30	Latency Quality Of Service Enable for Master 7
M7PR	29:28	Master 7 Priority
LQOSEN6	26	Latency Quality Of Service Enable for Master 6
M6PR	25:24	Master 6 Priority
LQOSEN5	22	Latency Quality Of Service Enable for Master 5
M5PR	21:20	Master 5 Priority
LQOSEN4	18	Latency Quality Of Service Enable for Master 4
M4PR	17:16	Master 4 Priority
LQOSEN3	14	Latency Quality Of Service Enable for Master 3
M3PR	13:12	Master 3 Priority
LQOSEN2	10	Latency Quality Of Service Enable for Master 2
M2PR	9:8	Master 2 Priority
LQOSEN1	6	Latency Quality Of Service Enable for Master 1
M1PR	5:4	Master 1 Priority
LQOSEN0	2	Latency Quality Of Service Enable for Master 0
M0PR	1:0	Master 0 Priority

PRS8.PRBSPriority B for Slave

Address: 0x448060C4
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN15	30	Latency Quality Of Service Enable for Master 15
M15PR	29:28	Master 15 Priority
LQOSEN14	26	Latency Quality Of Service Enable for Master 14
M14PR	25:24	Master 14 Priority
LQOSEN13	22	Latency Quality Of Service Enable for Master 13
M13PR	21:20	Master 13 Priority
LQOSEN12	18	Latency Quality Of Service Enable for Master 12
M12PR	17:16	Master 12 Priority
LQOSEN11	14	Latency Quality Of Service Enable for Master 11
M11PR	13:12	Master 11 Priority
LQOSEN10	10	Latency Quality Of Service Enable for Master 10
M10PR	9:8	Master 10 Priority
LQOSEN9	6	Latency Quality Of Service Enable for Master 9
M9PR	5:4	Master 9 Priority
LQOSEN8	2	Latency Quality Of Service Enable for Master 8
M8PR	1:0	Master 8 Priority

PRS9.PRASPriority A for Slave

Address: 0x448060C8
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN7	30	Latency Quality Of Service Enable for Master 7
M7PR	29:28	Master 7 Priority
LQOSEN6	26	Latency Quality Of Service Enable for Master 6
M6PR	25:24	Master 6 Priority
LQOSEN5	22	Latency Quality Of Service Enable for Master 5
M5PR	21:20	Master 5 Priority
LQOSEN4	18	Latency Quality Of Service Enable for Master 4
M4PR	17:16	Master 4 Priority
LQOSEN3	14	Latency Quality Of Service Enable for Master 3
M3PR	13:12	Master 3 Priority
LQOSEN2	10	Latency Quality Of Service Enable for Master 2
M2PR	9:8	Master 2 Priority
LQOSEN1	6	Latency Quality Of Service Enable for Master 1
M1PR	5:4	Master 1 Priority
LQOSEN0	2	Latency Quality Of Service Enable for Master 0
M0PR	1:0	Master 0 Priority

PRS9.PRBSPriority B for Slave

Address: 0x448060CC
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN15	30	Latency Quality Of Service Enable for Master 15
M15PR	29:28	Master 15 Priority
LQOSEN14	26	Latency Quality Of Service Enable for Master 14
M14PR	25:24	Master 14 Priority
LQOSEN13	22	Latency Quality Of Service Enable for Master 13
M13PR	21:20	Master 13 Priority
LQOSEN12	18	Latency Quality Of Service Enable for Master 12
M12PR	17:16	Master 12 Priority
LQOSEN11	14	Latency Quality Of Service Enable for Master 11
M11PR	13:12	Master 11 Priority
LQOSEN10	10	Latency Quality Of Service Enable for Master 10
M10PR	9:8	Master 10 Priority
LQOSEN9	6	Latency Quality Of Service Enable for Master 9
M9PR	5:4	Master 9 Priority
LQOSEN8	2	Latency Quality Of Service Enable for Master 8
M8PR	1:0	Master 8 Priority

PRS10.PRASPriority A for Slave

Address: 0x448060D0
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN7	30	Latency Quality Of Service Enable for Master 7
M7PR	29:28	Master 7 Priority
LQOSEN6	26	Latency Quality Of Service Enable for Master 6
M6PR	25:24	Master 6 Priority
LQOSEN5	22	Latency Quality Of Service Enable for Master 5
M5PR	21:20	Master 5 Priority
LQOSEN4	18	Latency Quality Of Service Enable for Master 4
M4PR	17:16	Master 4 Priority
LQOSEN3	14	Latency Quality Of Service Enable for Master 3
M3PR	13:12	Master 3 Priority
LQOSEN2	10	Latency Quality Of Service Enable for Master 2
M2PR	9:8	Master 2 Priority
LQOSEN1	6	Latency Quality Of Service Enable for Master 1
M1PR	5:4	Master 1 Priority
LQOSEN0	2	Latency Quality Of Service Enable for Master 0
M0PR	1:0	Master 0 Priority

PRS10.PRBSPriority B for Slave

Address: 0x448060D4
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN15	30	Latency Quality Of Service Enable for Master 15
M15PR	29:28	Master 15 Priority
LQOSEN14	26	Latency Quality Of Service Enable for Master 14
M14PR	25:24	Master 14 Priority
LQOSEN13	22	Latency Quality Of Service Enable for Master 13
M13PR	21:20	Master 13 Priority
LQOSEN12	18	Latency Quality Of Service Enable for Master 12
M12PR	17:16	Master 12 Priority
LQOSEN11	14	Latency Quality Of Service Enable for Master 11
M11PR	13:12	Master 11 Priority
LQOSEN10	10	Latency Quality Of Service Enable for Master 10
M10PR	9:8	Master 10 Priority
LQOSEN9	6	Latency Quality Of Service Enable for Master 9
M9PR	5:4	Master 9 Priority
LQOSEN8	2	Latency Quality Of Service Enable for Master 8
M8PR	1:0	Master 8 Priority

PRS11.PRASPriority A for Slave

Address: 0x448060D8
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN7	30	Latency Quality Of Service Enable for Master 7
M7PR	29:28	Master 7 Priority
LQOSEN6	26	Latency Quality Of Service Enable for Master 6
M6PR	25:24	Master 6 Priority
LQOSEN5	22	Latency Quality Of Service Enable for Master 5
M5PR	21:20	Master 5 Priority
LQOSEN4	18	Latency Quality Of Service Enable for Master 4
M4PR	17:16	Master 4 Priority
LQOSEN3	14	Latency Quality Of Service Enable for Master 3
M3PR	13:12	Master 3 Priority
LQOSEN2	10	Latency Quality Of Service Enable for Master 2
M2PR	9:8	Master 2 Priority
LQOSEN1	6	Latency Quality Of Service Enable for Master 1
M1PR	5:4	Master 1 Priority
LQOSEN0	2	Latency Quality Of Service Enable for Master 0
M0PR	1:0	Master 0 Priority

PRS11.PRBSPriority B for Slave

Address: 0x448060DC
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN15	30	Latency Quality Of Service Enable for Master 15
M15PR	29:28	Master 15 Priority
LQOSEN14	26	Latency Quality Of Service Enable for Master 14
M14PR	25:24	Master 14 Priority
LQOSEN13	22	Latency Quality Of Service Enable for Master 13
M13PR	21:20	Master 13 Priority
LQOSEN12	18	Latency Quality Of Service Enable for Master 12
M12PR	17:16	Master 12 Priority
LQOSEN11	14	Latency Quality Of Service Enable for Master 11
M11PR	13:12	Master 11 Priority
LQOSEN10	10	Latency Quality Of Service Enable for Master 10
M10PR	9:8	Master 10 Priority
LQOSEN9	6	Latency Quality Of Service Enable for Master 9
M9PR	5:4	Master 9 Priority
LQOSEN8	2	Latency Quality Of Service Enable for Master 8
M8PR	1:0	Master 8 Priority

PRS12.PRASPriority A for Slave

Address: 0x448060E0
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN7	30	Latency Quality Of Service Enable for Master 7
M7PR	29:28	Master 7 Priority
LQOSEN6	26	Latency Quality Of Service Enable for Master 6
M6PR	25:24	Master 6 Priority
LQOSEN5	22	Latency Quality Of Service Enable for Master 5
M5PR	21:20	Master 5 Priority
LQOSEN4	18	Latency Quality Of Service Enable for Master 4
M4PR	17:16	Master 4 Priority
LQOSEN3	14	Latency Quality Of Service Enable for Master 3
M3PR	13:12	Master 3 Priority
LQOSEN2	10	Latency Quality Of Service Enable for Master 2
M2PR	9:8	Master 2 Priority
LQOSEN1	6	Latency Quality Of Service Enable for Master 1
M1PR	5:4	Master 1 Priority
LQOSEN0	2	Latency Quality Of Service Enable for Master 0
M0PR	1:0	Master 0 Priority

PRS12.PRBSPriority B for Slave

Address: 0x448060E4
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
LQOSEN15	30	Latency Quality Of Service Enable for Master 15
M15PR	29:28	Master 15 Priority
LQOSEN14	26	Latency Quality Of Service Enable for Master 14
M14PR	25:24	Master 14 Priority
LQOSEN13	22	Latency Quality Of Service Enable for Master 13
M13PR	21:20	Master 13 Priority
LQOSEN12	18	Latency Quality Of Service Enable for Master 12
M12PR	17:16	Master 12 Priority
LQOSEN11	14	Latency Quality Of Service Enable for Master 11
M11PR	13:12	Master 11 Priority
LQOSEN10	10	Latency Quality Of Service Enable for Master 10
M10PR	9:8	Master 10 Priority
LQOSEN9	6	Latency Quality Of Service Enable for Master 9
M9PR	5:4	Master 9 Priority
LQOSEN8	2	Latency Quality Of Service Enable for Master 8
M8PR	1:0	Master 8 Priority

MRCRMaster Remap Control

Address: 0x44806100
Reset: 0x00000000
Access: read/write
Size: 32-bit

16 fields

Field	Bits	What it does
RCB15	15	Remap Command Bit for Master 15 `0` Disable remapped address decoding for master `1` Enable remapped address decoding for master
RCB14	14	Remap Command Bit for Master 14 `0` Disable remapped address decoding for master `1` Enable remapped address decoding for master
RCB13	13	Remap Command Bit for Master 13 `0` Disable remapped address decoding for master `1` Enable remapped address decoding for master
RCB12	12	Remap Command Bit for Master 12 `0` Disable remapped address decoding for master `1` Enable remapped address decoding for master
RCB11	11	Remap Command Bit for Master 11 `0` Disable remapped address decoding for master `1` Enable remapped address decoding for master
RCB10	10	Remap Command Bit for Master 10 `0` Disable remapped address decoding for master `1` Enable remapped address decoding for master
RCB9	9	Remap Command Bit for Master 9 `0` Disable remapped address decoding for master `1` Enable remapped address decoding for master
RCB8	8	Remap Command Bit for Master 8 `0` Disable remapped address decoding for master `1` Enable remapped address decoding for master
RCB7	7	Remap Command Bit for Master 7 `0` Disable remapped address decoding for master `1` Enable remapped address decoding for master
RCB6	6	Remap Command Bit for Master 6 `0` Disable remapped address decoding for master `1` Enable remapped address decoding for master
RCB5	5	Remap Command Bit for Master 5 `0` Disable remapped address decoding for master `1` Enable remapped address decoding for master
RCB4	4	Remap Command Bit for Master 4 `0` Disable remapped address decoding for master `1` Enable remapped address decoding for master
RCB3	3	Remap Command Bit for Master 3 `0` Disable remapped address decoding for master `1` Enable remapped address decoding for master
RCB2	2	Remap Command Bit for Master 2 `0` Disable remapped address decoding for master `1` Enable remapped address decoding for master
RCB1	1	Remap Command Bit for Master 1 `0` Disable remapped address decoding for master `1` Enable remapped address decoding for master
RCB0	0	Remap Command Bit for Master 0 `0` Disable remapped address decoding for master `1` Enable remapped address decoding for master

SFR0Special Function

Address: 0x44806110
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
SFR	31:0	Special Function Register

SFR1Special Function

Address: 0x44806114
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
SFR	31:0	Special Function Register

SFR2Special Function

Address: 0x44806118
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
SFR	31:0	Special Function Register

SFR3Special Function

Address: 0x4480611C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
SFR	31:0	Special Function Register

SFR4Special Function

Address: 0x44806120
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
SFR	31:0	Special Function Register

SFR5Special Function

Address: 0x44806124
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
SFR	31:0	Special Function Register

SFR6Special Function

Address: 0x44806128
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
SFR	31:0	Special Function Register

SFR7Special Function

Address: 0x4480612C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
SFR	31:0	Special Function Register

SFR8Special Function

Address: 0x44806130
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
SFR	31:0	Special Function Register

SFR9Special Function

Address: 0x44806134
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
SFR	31:0	Special Function Register

SFR10Special Function

Address: 0x44806138
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
SFR	31:0	Special Function Register

SFR11Special Function

Address: 0x4480613C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
SFR	31:0	Special Function Register

SFR12Special Function

Address: 0x44806140
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
SFR	31:0	Special Function Register

MEIERMaster Error Interrupt Enable

Address: 0x44806150
Reset: 0x00000000
Access: write only
Size: 32-bit

16 fields

Field	Bits	What it does
MERR15	15	Master 15 Access Error
MERR14	14	Master 14 Access Error
MERR13	13	Master 13 Access Error
MERR12	12	Master 12 Access Error
MERR11	11	Master 11 Access Error
MERR10	10	Master 10 Access Error
MERR9	9	Master 9 Access Error
MERR8	8	Master 8 Access Error
MERR7	7	Master 7 Access Error
MERR6	6	Master 6 Access Error
MERR5	5	Master 5 Access Error
MERR4	4	Master 4 Access Error
MERR3	3	Master 3 Access Error
MERR2	2	Master 2 Access Error
MERR1	1	Master 1 Access Error
MERR0	0	Master 0 Access Error

MEIDRMaster Error Interrupt Disable

Address: 0x44806154
Reset: 0x00000000
Access: write only
Size: 32-bit

16 fields

Field	Bits	What it does
MERR15	15	Master 15 Access Error
MERR14	14	Master 14 Access Error
MERR13	13	Master 13 Access Error
MERR12	12	Master 12 Access Error
MERR11	11	Master 11 Access Error
MERR10	10	Master 10 Access Error
MERR9	9	Master 9 Access Error
MERR8	8	Master 8 Access Error
MERR7	7	Master 7 Access Error
MERR6	6	Master 6 Access Error
MERR5	5	Master 5 Access Error
MERR4	4	Master 4 Access Error
MERR3	3	Master 3 Access Error
MERR2	2	Master 2 Access Error
MERR1	1	Master 1 Access Error
MERR0	0	Master 0 Access Error

MEIMRMaster Error Interrupt Mask

Address: 0x44806158
Reset: 0x00000000
Access: read only
Size: 32-bit

16 fields

Field	Bits	What it does
MERR15	15	Master 15 Access Error
MERR14	14	Master 14 Access Error
MERR13	13	Master 13 Access Error
MERR12	12	Master 12 Access Error
MERR11	11	Master 11 Access Error
MERR10	10	Master 10 Access Error
MERR9	9	Master 9 Access Error
MERR8	8	Master 8 Access Error
MERR7	7	Master 7 Access Error
MERR6	6	Master 6 Access Error
MERR5	5	Master 5 Access Error
MERR4	4	Master 4 Access Error
MERR3	3	Master 3 Access Error
MERR2	2	Master 2 Access Error
MERR1	1	Master 1 Access Error
MERR0	0	Master 0 Access Error

MESRMaster Error Status

Address: 0x4480615C
Reset: 0x00000000
Access: read only
Size: 32-bit

16 fields

Field	Bits	What it does
MERR15	15	Master 15 Access Error
MERR14	14	Master 14 Access Error
MERR13	13	Master 13 Access Error
MERR12	12	Master 12 Access Error
MERR11	11	Master 11 Access Error
MERR10	10	Master 10 Access Error
MERR9	9	Master 9 Access Error
MERR8	8	Master 8 Access Error
MERR7	7	Master 7 Access Error
MERR6	6	Master 6 Access Error
MERR5	5	Master 5 Access Error
MERR4	4	Master 4 Access Error
MERR3	3	Master 3 Access Error
MERR2	2	Master 2 Access Error
MERR1	1	Master 1 Access Error
MERR0	0	Master 0 Access Error

MEAR0Master Error Address

Address: 0x44806160
Reset: 0x00000000
Access: read only
Size: 32-bit

MEAR1Master Error Address

Address: 0x44806164
Reset: 0x00000000
Access: read only
Size: 32-bit

MEAR2Master Error Address

Address: 0x44806168
Reset: 0x00000000
Access: read only
Size: 32-bit

MEAR3Master Error Address

Address: 0x4480616C
Reset: 0x00000000
Access: read only
Size: 32-bit

MEAR4Master Error Address

Address: 0x44806170
Reset: 0x00000000
Access: read only
Size: 32-bit

MEAR5Master Error Address

Address: 0x44806174
Reset: 0x00000000
Access: read only
Size: 32-bit

MEAR6Master Error Address

Address: 0x44806178
Reset: 0x00000000
Access: read only
Size: 32-bit

MEAR7Master Error Address

Address: 0x4480617C
Reset: 0x00000000
Access: read only
Size: 32-bit

MEAR8Master Error Address

Address: 0x44806180
Reset: 0x00000000
Access: read only
Size: 32-bit

MEAR9Master Error Address

Address: 0x44806184
Reset: 0x00000000
Access: read only
Size: 32-bit

MEAR10Master Error Address

Address: 0x44806188
Reset: 0x00000000
Access: read only
Size: 32-bit

MEAR11Master Error Address

Address: 0x4480618C
Reset: 0x00000000
Access: read only
Size: 32-bit

MEAR12Master Error Address

Address: 0x44806190
Reset: 0x00000000
Access: read only
Size: 32-bit

MEAR13Master Error Address

Address: 0x44806194
Reset: 0x00000000
Access: read only
Size: 32-bit

MEAR14Master Error Address

Address: 0x44806198
Reset: 0x00000000
Access: read only
Size: 32-bit

MEAR15Master Error Address

Address: 0x4480619C
Reset: 0x00000000
Access: read only
Size: 32-bit