PIC32CK1012GC01100 ADC registers

The 31 registers of ADC (ADC Controller), from 0x45010000, with their reset value and every field. The PIC32CK1012GC01100 has 5256 registers in 62 peripherals, one page each.

ADC ADC Controller

CTRLACONTROL A REGISTER

Address: 0x45010000
Reset: 0x00000080
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
ONDEMAND	7	On Demand Control
RUNSTDBY	6	Run in Standby
AIPMPEN	4	Charge Pump Enable
ANAEN	2	Analog Enable
ENABLE	1	ENABLE BIT
SWRST	0	SOFTWARE RESET BIT

CTRLBCONTROL B REGISTER

Address: 0x45010004
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
SWCNVEN	15	Software Conversion Enable
STRGEN	11	Synchronous Trigger Enable
TRGSUSP	10	Trigger Suspend
LSWTRG	9	Level Global Trigger
GSWTRG	8	Global Software Trigger
SAMP	7	Channel Sample
RQCNVRT	6	Request Channel Convert
ADCORSEL	5:4	Software Trigger Core Select
ADCHSEL	3:0	Software Trigger Channel Select

CTRLCControl C Register

Address: 0x45010008
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
COREINTERLEAVED	30:28	Number of Core to Interleave Triggers
CNT	15:0	Clock Divider for Synchronous Trigger

CTRLDControl D Register

Address: 0x45010010
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
VREFSEL	30:28	Voltage Reference Select `0` AVDD and AVSS `1` External VREFH and AVSS
WKUPEXP	27:24	Wakeup cycles
ANLEN	23:20	Analog Channel Enable
CHNEN	19:16	Digital Channel Enable
CTLCKDIV	13:8	Control Clock Divider

CONFIG.CORCTRLSARCORE Control

Address: 0x45010020
Reset: 0x00000C00
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
ADCDIV	30:24	Division Ratio for SARCORE clock
SCNRTDS	22	SCAN Re-trigger Disable
STRGLVL	21	Scan Trigger Level Sensitivity
STRGSRC	19:16	SCAN trigger source selection `0` No Trigger (NOP) `1` Global Software Trigger `2` Global Level Software Trigger `4` STRIG Synchronous Trigger `5` ADC Trigger Event User 0 `6` ADC Trigger Event User 1 `7` ADC Trigger Event User 2 `8` ADC Trigger Event User 3 `9` ADC Trigger Event User 4 `10` ADC Trigger Event User 5 `11` ADC Trigger Event User 6 `12` ADC Trigger Event User 7 `13` ADC Trigger Event User 8 `14` ADC Trigger Event User 9 `15` ADC Trigger Event User 10
EIRQOVR	15	Interrupt Type Select
EIS	14:12	Early Interrupt Select
SELRES	11:10	Selects Resolution `0` 6 bits `1` 8 bits `2` 10 bits `3` 12 bits (default)
SAMC	9:0	Sample Count

CONFIG.CHNCFG1Channel Configuration 1 (LVL/CMPEN)

Address: 0x45010024
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
LVL	29:16	Channel Level
CHNCMPEN	13:0	Channel Comparator Enable

CONFIG.CHNCFG2Channel Configuration 2(FRACT/CSS)

Address: 0x45010028
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
FRACT	29:16	Channel Fractional
CSS	13:0	Channel SCAN Select

CONFIG.CHNCFG3Channel Configuration3 (SIGN/DIFF)

Address: 0x4501002C
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
SIGN	29:16	SIGN setting
DIFF4	4	Differential Mode enable for ADC module 0, analog input AIN4
DIFF2	2	Differential Mode enable for ADC module 0, analog input AIN2
DIFF0	0	Differential Mode enable for ADC module 0, analog input AIN0

CONFIG.CHNCFG4Channel Configuration 4 (TRGSRC)

Address: 0x45010030
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
TRGSRC6	27:24	Channel 6 Trigger Source `0` No Trigger (NOP) `1` Global Software Trigger `2` Global Level Software Trigger `3` SCANTRG - Scan Trigger `4` STRIG Synchronous Trigger `5` ADC Trigger Event User 0 `6` ADC Trigger Event User 1 `7` ADC Trigger Event User 2 `8` ADC Trigger Event User 3 `9` ADC Trigger Event User 4 `10` ADC Trigger Event User 5 `11` ADC Trigger Event User 6 `12` ADC Trigger Event User 7 `13` ADC Trigger Event User 8 `14` ADC Trigger Event User 9 `15` ADC Trigger Event User 10
TRGSRC5	23:20	Channel 5 Trigger Source `0` No Trigger (NOP) `1` Global Software Trigger `2` Global Level Software Trigger `3` SCANTRG - Scan Trigger `4` STRIG Synchronous Trigger `5` ADC Trigger Event User 0 `6` ADC Trigger Event User 1 `7` ADC Trigger Event User 2 `8` ADC Trigger Event User 3 `9` ADC Trigger Event User 4 `10` ADC Trigger Event User 5 `11` ADC Trigger Event User 6 `12` ADC Trigger Event User 7 `13` ADC Trigger Event User 8 `14` ADC Trigger Event User 9 `15` ADC Trigger Event User 10
TRGSRC4	19:16	Channel 4 Trigger Source `0` No Trigger (NOP) `1` Global Software Trigger `2` Global Level Software Trigger `3` SCANTRG - Scan Trigger `4` STRIG Synchronous Trigger `5` ADC Trigger Event User 0 `6` ADC Trigger Event User 1 `7` ADC Trigger Event User 2 `8` ADC Trigger Event User 3 `9` ADC Trigger Event User 4 `10` ADC Trigger Event User 5 `11` ADC Trigger Event User 6 `12` ADC Trigger Event User 7 `13` ADC Trigger Event User 8 `14` ADC Trigger Event User 9 `15` ADC Trigger Event User 10
TRGSRC3	15:12	Channel 3 Trigger Source `0` No Trigger (NOP) `1` Global Software Trigger `2` Global Level Software Trigger `3` SCANTRG - Scan Trigger `4` STRIG Synchronous Trigger `5` ADC Trigger Event User 0 `6` ADC Trigger Event User 1 `7` ADC Trigger Event User 2 `8` ADC Trigger Event User 3 `9` ADC Trigger Event User 4 `10` ADC Trigger Event User 5 `11` ADC Trigger Event User 6 `12` ADC Trigger Event User 7 `13` ADC Trigger Event User 8 `14` ADC Trigger Event User 9 `15` ADC Trigger Event User 10
TRGSRC2	11:8	Channel 2 Trigger Source `0` No Trigger (NOP) `1` Global Software Trigger `2` Global Level Software Trigger `3` SCANTRG - Scan Trigger `4` STRIG Synchronous Trigger `5` ADC Trigger Event User 0 `6` ADC Trigger Event User 1 `7` ADC Trigger Event User 2 `8` ADC Trigger Event User 3 `9` ADC Trigger Event User 4 `10` ADC Trigger Event User 5 `11` ADC Trigger Event User 6 `12` ADC Trigger Event User 7 `13` ADC Trigger Event User 8 `14` ADC Trigger Event User 9 `15` ADC Trigger Event User 10
TRGSRC1	7:4	Channel 1 Trigger Source `0` No Trigger (NOP) `1` Global Software Trigger `2` Global Level Software Trigger `3` SCANTRG - Scan Trigger `4` STRIG Synchronous Trigger `5` ADC Trigger Event User 0 `6` ADC Trigger Event User 1 `7` ADC Trigger Event User 2 `8` ADC Trigger Event User 3 `9` ADC Trigger Event User 4 `10` ADC Trigger Event User 5 `11` ADC Trigger Event User 6 `12` ADC Trigger Event User 7 `13` ADC Trigger Event User 8 `14` ADC Trigger Event User 9 `15` ADC Trigger Event User 10
TRGSRC0	3:0	Channel 0 Trigger Source `0` No Trigger (NOP) `1` Global Software Trigger `2` Global Level Software Trigger `3` SCANTRG - Scan Trigger `4` STRIG Synchronous Trigger `5` ADC Trigger Event User 0 `6` ADC Trigger Event User 1 `7` ADC Trigger Event User 2 `8` ADC Trigger Event User 3 `9` ADC Trigger Event User 4 `10` ADC Trigger Event User 5 `11` ADC Trigger Event User 6 `12` ADC Trigger Event User 7 `13` ADC Trigger Event User 8 `14` ADC Trigger Event User 9 `15` ADC Trigger Event User 10
TRGSRC7	31:28	Channel 7 Trigger Source `0` No Trigger (NOP) `1` Global Software Trigger `2` Global Level Software Trigger `3` SCANTRG - Scan Trigger `4` STRIG Synchronous Trigger `5` ADC Trigger Event User 0 `6` ADC Trigger Event User 1 `7` ADC Trigger Event User 2 `8` ADC Trigger Event User 3 `9` ADC Trigger Event User 4 `10` ADC Trigger Event User 5 `11` ADC Trigger Event User 6 `12` ADC Trigger Event User 7 `13` ADC Trigger Event User 8 `14` ADC Trigger Event User 9 `15` ADC Trigger Event User 10

CONFIG.CHNCFG5Channel Configuration 5 (TRGSRC)

Address: 0x45010034
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
TRGSRC14	27:24	Channel 14 Trigger Source `0` No Trigger (NOP) `1` Global Software Trigger `2` Global Level Software Trigger `3` SCANTRG - Scan Trigger `4` STRIG Synchronous Trigger `5` ADC Trigger Event User 0 `6` ADC Trigger Event User 1 `7` ADC Trigger Event User 2 `8` ADC Trigger Event User 3 `9` ADC Trigger Event User 4 `10` ADC Trigger Event User 5 `11` ADC Trigger Event User 6 `12` ADC Trigger Event User 7 `13` ADC Trigger Event User 8 `14` ADC Trigger Event User 9 `15` ADC Trigger Event User 10
TRGSRC13	23:20	Channel 13 Trigger Source `0` No Trigger (NOP) `1` Global Software Trigger `2` Global Level Software Trigger `3` SCANTRG - Scan Trigger `4` STRIG Synchronous Trigger `5` ADC Trigger Event User 0 `6` ADC Trigger Event User 1 `7` ADC Trigger Event User 2 `8` ADC Trigger Event User 3 `9` ADC Trigger Event User 4 `10` ADC Trigger Event User 5 `11` ADC Trigger Event User 6 `12` ADC Trigger Event User 7 `13` ADC Trigger Event User 8 `14` ADC Trigger Event User 9 `15` ADC Trigger Event User 10
TRGSRC12	19:16	Channel 12 Trigger Source `0` No Trigger (NOP) `1` Global Software Trigger `2` Global Level Software Trigger `3` SCANTRG - Scan Trigger `4` STRIG Synchronous Trigger `5` ADC Trigger Event User 0 `6` ADC Trigger Event User 1 `7` ADC Trigger Event User 2 `8` ADC Trigger Event User 3 `9` ADC Trigger Event User 4 `10` ADC Trigger Event User 5 `11` ADC Trigger Event User 6 `12` ADC Trigger Event User 7 `13` ADC Trigger Event User 8 `14` ADC Trigger Event User 9 `15` ADC Trigger Event User 10
TRGSRC11	15:12	Channel 11 Trigger Source `0` No Trigger (NOP) `1` Global Software Trigger `2` Global Level Software Trigger `3` SCANTRG - Scan Trigger `4` STRIG Synchronous Trigger `5` ADC Trigger Event User 0 `6` ADC Trigger Event User 1 `7` ADC Trigger Event User 2 `8` ADC Trigger Event User 3 `9` ADC Trigger Event User 4 `10` ADC Trigger Event User 5 `11` ADC Trigger Event User 6 `12` ADC Trigger Event User 7 `13` ADC Trigger Event User 8 `14` ADC Trigger Event User 9 `15` ADC Trigger Event User 10
TRGSRC10	11:8	Channel 10 Trigger Source `0` No Trigger (NOP) `1` Global Software Trigger `2` Global Level Software Trigger `3` SCANTRG - Scan Trigger `4` STRIG Synchronous Trigger `5` ADC Trigger Event User 0 `6` ADC Trigger Event User 1 `7` ADC Trigger Event User 2 `8` ADC Trigger Event User 3 `9` ADC Trigger Event User 4 `10` ADC Trigger Event User 5 `11` ADC Trigger Event User 6 `12` ADC Trigger Event User 7 `13` ADC Trigger Event User 8 `14` ADC Trigger Event User 9 `15` ADC Trigger Event User 10
TRGSRC9	7:4	Channel 9 Trigger Source `0` No Trigger (NOP) `1` Global Software Trigger `2` Global Level Software Trigger `3` SCANTRG - Scan Trigger `4` STRIG Synchronous Trigger `5` ADC Trigger Event User 0 `6` ADC Trigger Event User 1 `7` ADC Trigger Event User 2 `8` ADC Trigger Event User 3 `9` ADC Trigger Event User 4 `10` ADC Trigger Event User 5 `11` ADC Trigger Event User 6 `12` ADC Trigger Event User 7 `13` ADC Trigger Event User 8 `14` ADC Trigger Event User 9 `15` ADC Trigger Event User 10
TRGSRC8	3:0	Channel 8 Trigger Source `0` No Trigger (NOP) `1` Global Software Trigger `2` Global Level Software Trigger `3` SCANTRG - Scan Trigger `4` STRIG Synchronous Trigger `5` ADC Trigger Event User 0 `6` ADC Trigger Event User 1 `7` ADC Trigger Event User 2 `8` ADC Trigger Event User 3 `9` ADC Trigger Event User 4 `10` ADC Trigger Event User 5 `11` ADC Trigger Event User 6 `12` ADC Trigger Event User 7 `13` ADC Trigger Event User 8 `14` ADC Trigger Event User 9 `15` ADC Trigger Event User 10
TRGSRC15	31:28	Channel 15 Trigger Source `0` No Trigger (NOP) `1` Global Software Trigger `2` Global Level Software Trigger `3` SCANTRG - Scan Trigger `4` STRIG Synchronous Trigger `5` ADC Trigger Event User 0 `6` ADC Trigger Event User 1 `7` ADC Trigger Event User 2 `8` ADC Trigger Event User 3 `9` ADC Trigger Event User 4 `10` ADC Trigger Event User 5 `11` ADC Trigger Event User 6 `12` ADC Trigger Event User 7 `13` ADC Trigger Event User 8 `14` ADC Trigger Event User 9 `15` ADC Trigger Event User 10

CONFIG.CALCTRLSARCORE Calibration Value

Address: 0x45010038
Reset: 0x00000000
Access: read/write
Size: 32-bit

17 fields

Field	Bits	What it does
icmbf	29:28	Bias Current Common Mode Buffer
icmp_2	27:26	Bias Current Stage 2
icmp_1	25:24	Bias Current Stage 1
iadc_2	23:22	Current Consumption 2
iadc_1	21:20	Current Consumption 1
tclk_div	15:11	Test Clock Divider
t1_dly	10:9	Regen Latch Delay
sel_del	8	Scan Mode comp_out
dbg_sel	7	Debug Bus Select
en_rdac	6	Disable Power Cycling
dis_laz	5	Disable auto-zeroing
dis_saz	4	Disable auto-zeroing
dis_faz	3	Disable auto-zeroing
en_dither	2	Enable Dither
en_cmbf	0	Enable Common Mode Buffer
CALBITS	31:0	Calibration Values
en_ext_bias	31	Dsiable Internal Bias Circuit

CONFIG.EVCTRLEvent Control

Address: 0x4501003C
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
CMPEO	5	Comparator Window Event Out
RESRDYEO	4	Result Ready Event Out
STARTINV	3	Start Conversion Invert
STARTEI	0	Start Event conversion input enable

CMPCTRLComparator Control

Address: 0x450100B0
Reset: 0x00000000
Access: read/write
Size: 32-bit

8 fields

Field	Bits	What it does
IEHIHI	29	Enable VAL >= CMPHI
IEHILO	28	Enable VAL < CMPHI
ADCMPHI	27:16	High Limit of Digital Comparator
IEBTWN	15	Enable CMPLO <= VAL < CMPHI
IELOHI	14	Enable VAL >= CMPLO
IELOLO	13	Enable VAL < CMPLO
CMPEN	12	Comparator Enable
ADCMPLO	11:0	Low Limit of Digital Comparator

FLTCTRLFilter Control

Address: 0x450100C0
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
FLTCHNID	13:10	Channel ID
FLTEN	8	Filter Enable
DATA16EN	4	16bit Averaging Mode
FMODE	3	Filter Mode
OVRSAM	2:0	Oversampling Ratio `0` (If FMODE is 0) 4 samples (shift sum 1 bit to right, output data is 13-bits) / (If FMODE is 1) 2 samples to be averaged `1` (If FMODE is 0) 16 samples (shift sum 2 bits to right, output data is 14-bits) / (If FMODE is 1) 4 samples to be averaged `2` (If FMODE is 0) 64 samples (shift sum 3 bits to right, output data is 15-bits) / (If FMODE is 1) 8 samples to be averaged `3` (If FMODE is 0) 256 samples (shift sum 4 bits to right, output data is 16-bits) / (If FMODE is 1) 16 samples to be averaged `4` (If FMODE is 0) 2 samples (shift sum 0 bits to right, output data is 12.1 format) / (If FMODE is 1) 32 samples to be averaged `5` (If FMODE is 0) 8 samples (shift sum 1 bit to right, output data is 13.1 format) / (If FMODE is 1) 64 samples to be averaged `6` (If FMODE is 0) 32 samples (shift sum 2 bits to right, output data is 14.1 format) / (If FMODE is 1) 128 samples to be averaged `7` (If FMODE is 0) 128 samples (shift sum 3 bits to right, output data is 15.1 format) / (If FMODE is 1) 256 samples to be averaged

CORCHDATAIDChannel Ready DATA ID

Address: 0x450100D0
Reset: 0x00000000
Access: read/write
Size: 32-bit

2 fields

Field	Bits	What it does
CORDYID	5:4	Core Read ID
CHRDYID	3:0	Channel Read ID

CHRDYDATChannel Ready Data Register

Address: 0x450100D4
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
FRACT	27	Fractional Setting
SIGN	26	Sign Setting
DIFF	25	Differential Setting
LVL	24	Level Setting
CHRDYDAT	15:0	Channel Output Data

PFFDATAAPB FIFO Output Data

Address: 0x450100D8
Reset: 0x00000000
Access: read only
Size: 32-bit

6 fields

Field	Bits	What it does
PFFFRACT	23	Fractional Setting from APB FIFO
PFFSIGN	22	Channel Sign from the APB FIFO
PFFCORID	21:20	Core ID from APB FIFO
PFFCHNID	19:16	Channel ID from APB FIFO
PFFDATA	15:0	SARCORE Conversion data from the APB FIFO
PFFCNT	31:24	Current Data Entries in APB FIFO

DMABASEDMA Sample Base Address

Address: 0x450100DC
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DMABASE	31:0	DMA Sample Value Base Address

DMACTRLDMA Control Register

Address: 0x450100E0
Reset: 0x00000000
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
DMABL	10:8	DMA System RAM Buffer Length
DMACR	7:4	DMA CORE Enables
DMAEN	1	DMA Enable

PFFCTRLAPB FIFO Control Register

Address: 0x450100E4
Reset: 0x00000000
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
PFFRDYDM	16	DMA APB FIFO Data Ready `0` Selects CTLINTFLAG.PFFHFUL for the ADC DMA PFFRDY trigger signal to the DMAC `1` Selects CTLINTFLAG.PFFRDY for the ADC DMA PFFRDY trigger signal to the DMAC
PFFCR	7:4	APB CORE FIFO Enable
PFFEN	1	APB FIFO Enable

SYNCBUSYCORE SYNC Busy Status Register

Address: 0x450100E8
Reset: 0x00000000
Access: read only
Size: 32-bit

3 fields

Field	Bits	What it does
CTRLB	2	CTRLB sync busy
ENABLE	1	Enable bit Sync Busy
SWRST	0	Software Reset Sync Busy

DMAINTENCLRDMA Interrupt Enable Clear

Address: 0x450100F0
Reset: 0x00000000
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
SOVFL	16	Synchonizer Overflow
RBF	7:4	Ram Buffer B Full
RAF	3:0	Ram Buffer A Full

DMAINTSETDMA Interrupt Enable Set

Address: 0x450100F4
Reset: 0x00000000
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
SOVFL	16	Synchonizer Overflow
RBF	7:4	Ram Buffer B Full
RAF	3:0	Ram Buffer A Full

DMAINTFLAGDMA Interrupt Flag and Status

Address: 0x450100F8
Reset: 0x00000000
Access: read/write
Size: 32-bit

6 fields

Field	Bits	What it does
DMAERR	17	DMA Bus Error
SOVFL	16	Synchronizer overflow
EBF	15:12	Ram Buffer B Overflow Error
EAF	11:8	Ram Buffer A Overflow Error
RBF	7:4	Ram Buffer B Full
RAF	3:0	Ram Buffer A Full

CTLINTENSETCORE Controller Interrupt Enable Set

Address: 0x450100FC
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
PFFHFUL	11	APB FIFO Half Full
PFFRDY	10	APB FIFO Ready
PFFOVF	9	APB FIFO Overflow
PFFUNF	8	APB FIFO Underflow
VREFRDY	7	VREF Ready
VREFUPD	6	VREF update
CRRDY	3:0	Core Ready

CTLINTENCLRCORE Controller Interrupt Enable Clear

Address: 0x45010100
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
PFFHFUL	11	APB FIFO Half Full
PFFRDY	10	APB FIFO Ready
PFFOVF	9	APB FIFO overflow
PFFUNF	8	APB FIFO underflow
VREFRDY	7	VREF Ready
VREFUPD	6	VREF Update
CRRDY	3:0	Core Ready Disable

CTLINTFLAGCORE Controller Interrupt Flags

Address: 0x45010104
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
PFFHFUL	11	APB FIFO Half Full
PFFRDY	10	APB FIFO Ready
PFFOVF	9	APB FIFO overflow
PFFUNF	8	APB FIFO underflow
VREFRDY	7	VREF Ready
VREFUPD	6	VREF update
CRRDY	3:0	Core Ready

INTENCLRInterrupt Enable Clear

Address: 0x45010120
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
CHRDY	27:12	Channel Ready Disable
EOSRDY	11	Endo of Scan Disable
CHNERRC	10	Channel Overwrite Error Disable
FLTRDY	9	Filter Ready Disable
CHRDYC	8	Core Current Channel Disable
SOVFL	7	Synchonizer Overflow Disable
CMPHIT	4	Compare Hit Disable

INTENSETInterrupt Enable Set

Address: 0x45010124
Reset: 0x00000000
Access: read/write
Size: 32-bit

7 fields

Field	Bits	What it does
EOSRDY	11	End of Scan Enable
CHNERRC	10	Channel Overwrite Enable
FLTRDY	9	Filter Ready Enable
CHRDYC	8	Current Channel Ready Enable
SOVFL	7	Synchronizer Overflow Enable
CMPHIT	4	Compare Hit Enable
CHRDY	31:16	Channel Ready Enable

INTFLAGInterrupt Flags

Address: 0x45010128
Reset: 0x00000000
Access: read/write
Size: 32-bit

9 fields

Field	Bits	What it does
CRDYID	15:12	Channel Ready ID
EOSRDY	11	End of Scan Ready
CHNERRC	10	Channel Overwrite Error
FLTRDY	9	Filter Ready
CHRDYC	8	Current Channel Ready
SOVFL	7	Synchronizer Overflow
CMPHIT	4	Compare Hit
CMPINTID	3:0	Compare Channel ID
CHRDY	31:16	Channel Ready

DBGCTRLDebug Control Register

Address: 0x45010168
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DBGRUN	0	Debug Running State