PIC32CK1012SG00064 DMA1 registers The 160 registers of DMA1 (Direct Memory Access Controller), from 0x44804000, with their reset value and every field. The PIC32CK1012SG00064 has 5596 registers in 69 peripherals, one page each.
DMA1 Direct Memory Access Controller CTRLADMA CONTROL A REGISTER
Address 0x44804000
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does ENABLE 1 DMA Enable
CTRLBDMA CONTROL B REGISTER
Address 0x44804004
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does QOS3 17:16 Priority Group 3 Quality Of Service Control0 QoS level is 0 (lowest)1 QoS level is 1 (lower)2 QoS level is 2 (medium)3 QoS level is 3 (high) QOS2 9:8 Priority Group 2 Quality Of Service Control0 QoS level is 0 (lowest)1 QoS level is 1 (lower)2 QoS level is 2 (medium)3 QoS level is 3 (high) QOS1 1:0 Priority Group 1 Quality Of Service Control0 QoS level is 0 (lowest)1 QoS level is 1 (lower)2 QoS level is 2 (medium)3 QoS level is 3 (high)
DBGCTRLDEBUG CONTROL REGISTER
Address 0x44804008
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DBGRUN 0 Debug Run
CRCPOLYADMA CRC POLYNOMIAL A REGISTER
Address 0x4480400C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does POLYA 31:0 CRC Polynomial Coefficients A Register
CRCPOLYBDMA CRC POLYNOMIAL B REGISTER
Address 0x44804010
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does POLYB 31:0 CRC Polynomial Coefficients B Register
INTSTAT3DMA INTERRUPT PRIORITY 3 STATUS REGISTER
Address 0x44804018
Reset 0x00000000
Access read only
Size 32-bit 8 fields
Field Bits What it does CH7 7 DMA Channel active interrupt at priority 3 CH6 6 DMA Channel active interrupt at priority 3 CH5 5 DMA Channel active interrupt at priority 3 CH4 4 DMA Channel active interrupt at priority 3 CH3 3 DMA Channel active interrupt at priority 3 CH2 2 DMA Channel active interrupt at priority 3 CH1 1 DMA Channel active interrupt at priority 3 CH0 0 DMA Channel active interrupt at priority 3
INTSTAT2DMA INTERRUPT PRIORITY 2 STATUS REGISTER
Address 0x4480401C
Reset 0x00000000
Access read only
Size 32-bit 8 fields
Field Bits What it does CH7 7 DMA Channel active interrupt at priority 2 CH6 6 DMA Channel active interrupt at priority 2 CH5 5 DMA Channel active interrupt at priority 2 CH4 4 DMA Channel active interrupt at priority 2 CH3 3 DMA Channel active interrupt at priority 2 CH2 2 DMA Channel active interrupt at priority 2 CH1 1 DMA Channel active interrupt at priority 2 CH0 0 DMA Channel active interrupt at priority 2
INTSTAT1DMA INTERRUPT PRIORITY 1 STATUS REGISTER
Address 0x44804020
Reset 0x00000000
Access read only
Size 32-bit 8 fields
Field Bits What it does CH7 7 DMA Channel active interrupt at priority 1 CH6 6 DMA Channel active interrupt at priority 1 CH5 5 DMA Channel active interrupt at priority 1 CH4 4 DMA Channel active interrupt at priority 1 CH3 3 DMA Channel active interrupt at priority 1 CH2 2 DMA Channel active interrupt at priority 1 CH1 1 DMA Channel active interrupt at priority 1 CH0 0 DMA Channel active interrupt at priority 1
CHANNEL0.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x44804050
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL0.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x44804054
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE0, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 3 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL0.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x44804058
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Block Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger3 Event aborts Linked List operation and Block Transfer
CHANNEL0.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x4480405C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL0.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x44804060
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL0.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x44804064
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL0.CHSSACHANNEL SOURCE START ADDRESS
Address 0x44804068
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL0.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x4480406C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL0.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x44804070
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL0.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x44804074
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL0.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x44804078
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL0.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x4480407C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL0.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x44804080
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL0.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x44804084
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL0.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x44804088
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL0.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x4480408C
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL0.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x44804090
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL0.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x44804094
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL0.CHSTATCHANNEL STATUS REGISTER
Address 0x44804098
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
CHANNEL1.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x448040A0
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL1.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x448040A4
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE0, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 3 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL1.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x448040A8
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Block Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger3 Event aborts Linked List operation and Block Transfer
CHANNEL1.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x448040AC
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL1.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x448040B0
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL1.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x448040B4
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL1.CHSSACHANNEL SOURCE START ADDRESS
Address 0x448040B8
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL1.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x448040BC
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL1.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x448040C0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL1.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x448040C4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL1.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x448040C8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL1.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x448040CC
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL1.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x448040D0
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL1.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x448040D4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL1.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x448040D8
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL1.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x448040DC
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL1.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x448040E0
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL1.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x448040E4
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL1.CHSTATCHANNEL STATUS REGISTER
Address 0x448040E8
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
CHANNEL2.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x448040F0
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL2.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x448040F4
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE0, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 3 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL2.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x448040F8
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Block Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger3 Event aborts Linked List operation and Block Transfer
CHANNEL2.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x448040FC
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL2.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x44804100
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL2.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x44804104
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL2.CHSSACHANNEL SOURCE START ADDRESS
Address 0x44804108
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL2.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x4480410C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL2.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x44804110
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL2.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x44804114
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL2.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x44804118
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL2.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x4480411C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL2.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x44804120
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL2.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x44804124
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL2.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x44804128
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL2.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x4480412C
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL2.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x44804130
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL2.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x44804134
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL2.CHSTATCHANNEL STATUS REGISTER
Address 0x44804138
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
CHANNEL3.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x44804140
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL3.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x44804144
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE0, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 3 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL3.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x44804148
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Block Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger3 Event aborts Linked List operation and Block Transfer
CHANNEL3.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x4480414C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL3.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x44804150
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL3.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x44804154
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL3.CHSSACHANNEL SOURCE START ADDRESS
Address 0x44804158
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL3.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x4480415C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL3.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x44804160
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL3.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x44804164
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL3.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x44804168
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL3.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x4480416C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL3.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x44804170
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL3.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x44804174
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL3.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x44804178
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL3.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x4480417C
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL3.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x44804180
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL3.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x44804184
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL3.CHSTATCHANNEL STATUS REGISTER
Address 0x44804188
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
CHANNEL4.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x44804190
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL4.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x44804194
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE0, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 3 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL4.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x44804198
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Block Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger3 Event aborts Linked List operation and Block Transfer
CHANNEL4.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x4480419C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL4.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x448041A0
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL4.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x448041A4
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL4.CHSSACHANNEL SOURCE START ADDRESS
Address 0x448041A8
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL4.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x448041AC
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL4.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x448041B0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL4.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x448041B4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL4.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x448041B8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL4.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x448041BC
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL4.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x448041C0
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL4.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x448041C4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL4.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x448041C8
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL4.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x448041CC
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL4.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x448041D0
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL4.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x448041D4
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL4.CHSTATCHANNEL STATUS REGISTER
Address 0x448041D8
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
CHANNEL5.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x448041E0
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL5.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x448041E4
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE0, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 3 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL5.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x448041E8
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Block Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger3 Event aborts Linked List operation and Block Transfer
CHANNEL5.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x448041EC
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL5.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x448041F0
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL5.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x448041F4
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL5.CHSSACHANNEL SOURCE START ADDRESS
Address 0x448041F8
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL5.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x448041FC
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL5.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x44804200
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL5.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x44804204
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL5.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x44804208
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL5.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x4480420C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL5.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x44804210
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL5.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x44804214
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL5.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x44804218
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL5.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x4480421C
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL5.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x44804220
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL5.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x44804224
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL5.CHSTATCHANNEL STATUS REGISTER
Address 0x44804228
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
CHANNEL6.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x44804230
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL6.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x44804234
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE0, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 3 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL6.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x44804238
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Block Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger3 Event aborts Linked List operation and Block Transfer
CHANNEL6.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x4480423C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL6.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x44804240
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL6.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x44804244
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL6.CHSSACHANNEL SOURCE START ADDRESS
Address 0x44804248
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL6.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x4480424C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL6.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x44804250
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL6.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x44804254
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL6.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x44804258
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL6.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x4480425C
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL6.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x44804260
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL6.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x44804264
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL6.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x44804268
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL6.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x4480426C
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL6.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x44804270
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL6.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x44804274
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL6.CHSTATCHANNEL STATUS REGISTER
Address 0x44804278
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
CHANNEL7.CHCTRLACHANNEL CONTROL REGISTER A
Address 0x44804280
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RUNSTDBY 24 Run In Standby SWFRC 16 Software Forced Trigger LLEN 8 Linked List Enable ENABLE 0 Channel Enable
CHANNEL7.CHCTRLBCHANNEL CONTROL REGISTER B
Address 0x44804284
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does CASTEN 29 Cell Auto Start Enable of Ensuing Transfers for this channel PATEN 26 Channel Pattern Match Abort Enable. PATLEN 25 Pattern Match Length PIGNEN 24 Enable Pattern Ignore Byte TRIG 23:16 Trigger that can Start a Channel Transfer BYTORD 15:14 Byte Order0 Bytes are processed AS IS1 Bytes are swapped as: BYTE3 to BYTE0, BYTE2 to BYTE1, BYTE1 to BYTE2, and BYTE0 to BYTE32 Bytes are swapped as: BYTE3 to BYTE1, BYTE2 to BYTE0, BYTE1 to BYTE3, and BYTE0 to BYTE23 Bytes are swapped as: BYTE3 to BYTE2, BYTE2 to BYTE3, BYTE1 to BYTE0, and BYTE0 to BYTE1 WBOEN 13 Write Byte Order Enable PRI 9:8 Channel Priority level.0 Channel Priority is 11 Channel Priority is 22 Channel Priority is 3 (HIGHEST) RAS 6:4 Channel Read Address Sequence0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer WAS 2:0 Channel Write Address Sequence.0 Incrementing Address+1 with Transfers of Byte Operands1 Incrementing Address+2 with Transfers of HalfWord Operands2 Auto Increment Address and Transfer Size3 Fixed Byte Address (Single Byte Address with Enable Based upon 2 LSBs)4 Fixed Address of HalfWord Operand (Single HalfWord Aligned Address)5 Fixed Address Word Burst Transfer CRCEN 31 CRC Enable bit
CHANNEL7.CHEVCTRLCHANNEL EVENT CONTROL REGISTER
Address 0x44804288
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does EVOE 7 Channel Event Output Enable (0: disable; 1: enable) EVSTRIE 6 Channel Start Event Input Enable (0: disable; 1:enable) EVAUXIE 5 Channel Auxiliary Event Enable (0: disable; 1: enable) EVOMODE 3:2 Channel Event Output Mode0 Generate a channel event strobe for 1 clock cycle at the end of block transfer1 Generate a channel event strobe for 1 clock cycle at the end of cell transfer2 Generate a channel event strobe from start event trigger to the completion of cell transfer read3 Generate a channel event strobe from start event trigger to the completion of cell transfer write EVAUXACT 1:0 Channel Auxiliary Event Input Action0 Event Aborts Block Transfer1 Event Increments Channel Priority2 Event acts as a Conditional Trigger3 Event aborts Linked List operation and Block Transfer
CHANNEL7.CHINTENCLRCHANNEL INTERRUPT ENABLE CLEAR REGISTER
Address 0x4480428C
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 Clear Linked List Done Interrupt Enable BH 4 Clear Block Transfer Half Complete Interrupt Enable BC 3 Clear Cell Transfer Complete Interrupt Enable CC 2 Clear Cell Transfer Complete Interrupt Enable TA 1 Clear Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL7.CHINTENSETCHANNEL INTERRUPT ENABLE SET REGISTER
Address 0x44804290
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does LL 5 set Linked List Done Interrupt Enable BH 4 set Block Transfer Half Complete Interrupt Enable BC 3 set Cell Transfer Complete Interrupt Enable CC 2 set Cell Transfer Complete Interrupt Enable TA 1 Set Transfer Abort Interrupt Enable SD 0 Channel Event Output Enable
CHANNEL7.CHINTFCHANNEL INTERRUPT FLAG REGISTER
Address 0x44804294
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does RDE 18 Read Error Flag (0: none; 1: Read Error) WRE 17 Write Error Flag (0: none; 1: Write Error) LL 5 Linked List Done Interrupt Flag (0: none; 1: done) BH 4 Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete) BC 3 Block Transfer Complete Interrupt Flag (0: none; 1:complete;) CC 2 Cell Transfer Complete Interrupt Flag (0: none ; 1: complete) TA 1 Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted) SD 0 Start Detected Interrupt Flag (0: none ; 1: Start Detected)
CHANNEL7.CHSSACHANNEL SOURCE START ADDRESS
Address 0x44804298
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSA 31:0 Channel Source Start Address
CHANNEL7.CHDSACHANNEL DESTINATION START ADDRESS
Address 0x4480429C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSA 31:0 Channel Destination Start Address
CHANNEL7.CHSSTRDCHANNEL SOURCE CELL STRIDE SIZE REGISTER
Address 0x448042A0
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does SSTRD 15:0 Source Cell Stride Size
CHANNEL7.CHDSTRDCHANNEL DESTINATION CELL STRIDE SIZE REGISTER
Address 0x448042A4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DSTRD 15:0 Destination Cell Stride Size
CHANNEL7.CHXSIZCHANNEL TRANSFER SIZE REGISTER
Address 0x448042A8
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does CSZ 9:0 Cell transfer size in bytes. BLKSZ 31:16 Block transfer size in bytes.
CHANNEL7.CHPDATCHANNEL PATTERN MATCH DATA
Address 0x448042AC
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does PDAT 15:0 Channel Pattern Match Data PIGN 31:24 Channel Pattern Ignore Value
CHANNEL7.CHCTRLCRCCHANNEL CONTROL CRC
Address 0x448042B0
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does CRCRIN 7 CRC Reflect Input Selection CRCROUT 6 CRC Reflected Output Mode CRCXOR 5 CRC XOR Mode CRCAPP 3 CRC Append Mode CRCMD 2:0 CRC/Checksum Mode0 Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI1 Normal (0x1021) CRC-16-CCITT2 CRC-16 based on polynomial provided in CRCPOLYA (POLYA[15:0]) register3 CRC-16 based on polynomial provided in CRCPOLYB (POLYB[15:0]) register4 Normal (0x04C11DB7) CRC-325 CRC-32 based on polynomial provided in CRCPOLYA register6 CRC-32 based on polynomial provided in CRCPOLYB register7 Calculate IP header checksum
CHANNEL7.CHCRCDATCHANNEL CRC/CHECKSUM DATA REGISTER
Address 0x448042B4
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CRCDAT 31:0 CRC Data
CHANNEL7.CHNXTCHANNEL NEXT DESCRIPTOR ADDRESS POINTER
Address 0x448042B8
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does NXT 31:0 Channel Address Pointer to Next Descriptor
CHANNEL7.CHLLCFGSTATCHANNEL LINKED LIST CONFIGURATION STATUS REGISTER
Address 0x448042BC
Reset 0x00000000
Access read only
Size 32-bit 10 fields
Field Bits What it does CRCDAT 9 CRC Data Descriptor Load CTRLCRC 8 Control CRC Descriptor Load PDAT 7 Match Pattern Descriptor Load XSIZ 6 Transfer Size Descriptor Load DSTRD 5 Destination Cell Stride Size Descriptor Load SSTRD 4 Source Cell Stride Size Descriptor Load DSA 3 Destination Start Address Descriptor Load SSA 2 Source Start Address Descriptor Load EVCTRL 1 EVCTRL Register Descriptor Load CTRLB 0 CTRLB Register Descriptor Load
CHANNEL7.CHSTATBCCHANNEL STATUS BLOCK COUNT REGISTER
Address 0x448042C0
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does BBTC 16:0 Bytes Transfered in the Block Counter
CHANNEL7.CHSTATCCCHANNEL STATUS CELL COUNT REGISTER
Address 0x448042C4
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CBTC 10:0 Bytes Transfered in the Cell Counter
CHANNEL7.CHSTATCHANNEL STATUS REGISTER
Address 0x448042C8
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does DREAD 2 Descriptor Read Status Bit (0: not read or not avail, 1: read and loaded) CELLBUSY 1 Channel Cell Transfer Busy Status Bit (0: none; 1: busy) BLKBUSY 0 Channel Block Transfer Busy Status Bit (0: none; 1: busy)
BETA