PIC32CK1012SG00064 FPU registers

The 6 registers of FPU (Floating-point Extension), from 0xE000EF34, with their reset value and every field. The PIC32CK1012SG00064 has 5596 registers in 69 peripherals, one page each.

FPU Floating-point Extension

FPCCRFloating-Point Context Control Register

Address: 0xE000EF34
Reset: 0x00000000
Access: read/write
Size: 32-bit

17 fields

Field	Bits	What it does
LSPEN	30	Automatic lazy FP context save enable
LSPENS	29	LSPEN field writeable only from Secure state
CLRONRET	28	Clear FP caller saved registers enable
CLRONRETS	27	CLRONRET field writeable only from Secure state
TS	26	Treat FP registers as Secure enable
UFRDY	10	UsageFault exception set to pending
SPLIMVIOL	9	FP context violates the stack pointer limit
MONRDY	8	DebugMonitor exception set to pending
SFRDY	7	SecureFault exception set to pending
BFRDY	6	BusFault exception set to pending
MMRDY	5	MemManage exception set to pending
HFRDY	4	HardFault exception set to pending
THREAD	3	Thread mode when FP stack frame allocated
S	2	Security status of FP context
USER	1	Privilege level when FP stack frame allocated
LSPACT	0	Lazy preservation of FP state active
ASPEN	31	Automatic FP context save enable

FPCARFloating-Point Context Address Register

Address: 0xE000EF38
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
ADDRESS	31:3	Address for FP registers push to exception stack

FPDSCRFloating-Point Default Status Control Register

Address: 0xE000EF3C
Reset: 0x00000000
Access: read/write
Size: 32-bit

4 fields

Field	Bits	What it does
AHP	26	Alternative half-precision default value
DN	25	NaN default value
FZ	24	Flush-to-zero default value
RMode	23:22	Rounding mode default value

MVFR0Media and VFP Feature Register 0

Address: 0xE000EF40
Reset: 0x00000000
Access: read only
Size: 32-bit

6 fields

Field	Bits	What it does
FPSqrt	23:20	FP square root operations support
FPDivide	19:16	FP divide operations support
FPDP	11:8	FP double-precision operations support `2` Supported
FPSP	7:4	FP single-precision operations support `2` Supported
SIMDReg	3:0	Size of FP register file `1` 16 x 64-bit registers
FPRound	31:28	All FP rounding modes support

MVFR1Media and VFP Feature Register 1

Address: 0xE000EF44
Reset: 0x00000000
Access: read only
Size: 32-bit

4 fields

Field	Bits	What it does
FPHP	27:24	Floating-point half-precision conversion instructions `1` Half-precision to single-precision supported `2` Half-precision to single- and double-precision supported
FPDNaN	7:4	Propagation of NaN values support
FPFtZ	3:0	Floating-point subnormals flush-to-zero
FMAC	31:28	Fused multiply accumulate instructions

MVFR2Media and VFP Feature Register 2

Address: 0xE000EF48
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
FPMisc	7:4	Floating-point miscellaneous features support `4` Selection, directed conversion to integer, VMINNM, and VMAXNM supported