PIC32CK1012SG00064 SCB registers

The 36 registers of SCB (System Control Block), from 0xE000ED00, with their reset value and every field. The PIC32CK1012SG00064 has 5596 registers in 69 peripherals, one page each.

SCB System Control Block

CPUIDCPUID base register

Address
0xE000ED00
Reset
0x00000000
Access
read only
Size
32-bit
5 fields
FieldBitsWhat it does
Variant23:20Variant number
Architecture19:16Architecture version, 0xC=ARMv8-M Base Line, 0xF=ARMv8-M Main Line
PartNo15:4Part number, 0xD21=Cortex-M33
Revision3:0Revision number
Implementer31:24Implementer code, ARM=0x41

ICSRInterrupt Control and State Register

Address
0xE000ED04
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
PENDNMICLR30Pend NMI clear
PENDSVSET28Pend PendSV set
  • 0 Write: no effect; read: PendSV exception is not pending
  • 1 Write: changes PendSV exception state to pending; read: PendSV exception is pending
PENDSVCLR27Pend PendSV clear
  • 0 No effect
  • 1 Removes the pending state from the PendSV exception
PENDSTSET26Pend SysTick set
  • 0 Write: no effect; read: SysTick exception is not pending
  • 1 Write: changes SysTick exception state to pending; read: SysTick exception is pending
PENDSTCLR25Pend SysTick clear
  • 0 No effect
  • 1 Removes the pending state from the SysTick exception
ISRPREEMPT23Interrupt preempt
ISRPENDING22Interrupt pending
VECTPENDING20:12Vector pending
RETTOBASE11Return to base
VECTACTIVE8:0Vector active
PENDNMISET31Pend NMI set
  • 0 Write: no effect; read: NMI exception is not pending
  • 1 Write: changes NMI exception state to pending; read: NMI exception is pending

VTORVector Table Offset Register

Address
0xE000ED08
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TBLOFF31:7Vector table base offset

AIRCRApplication Interrupt and Reset Control Register

Address
0xE000ED0C
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
ENDIANNESS15Data Endianness, 0=little, 1=big
  • 0 Little-endian
  • 1 Big-endian
PRIS14Prioritize Secure Exceptions
  • 0 Priority ranges of Secure and Non-secure exceptions are identical
  • 1 Non-secure exceptions are de-prioritized
BFHFNMINS13BusFault, HardFault and NMI Non-secure enable
  • 0 BusFault, HardFault, and NMI are Secure
  • 1 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault
SYSRESETREQS3System Reset Request Secure only
  • 0 SYSRESETREQ functionality is available to both Security states
  • 1 SYSRESETREQ functionality is only available to Secure state
SYSRESETREQ2System Reset Request
  • 0 Do not request a system reset
  • 1 Request a system reset
VECTCLRACTIVE1Debug: Clear Active State
  • 0 Do not clear active state
  • 1 Clear active state
VECTKEY31:16Register Key (0x05FA)

SCRSystem Control Register

Address
0xE000ED10
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
SEVONPEND4Send Event on Pending bit
  • 0 Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded
  • 1 Enabled events and all interrupts, including disabled interrupts, can wakeup the processor
SLEEPDEEPS3Sleep deep secure
SLEEPDEEP2Sleep deep
  • 0 Sleep
  • 1 Deep sleep
SLEEPONEXIT1Sleep on exit
  • 0 O not sleep when returning to Thread mode
  • 1 Enter sleep, or deep sleep, on return from an ISR

CCRConfiguration and Control Register

Address
0xE000ED14
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
BP18Branch prediction enable
IC17Instruction cache enable
DC16Data cache enable
STKOFHFNMIGN10Stack overflow in HardFault and NMI ignore
BFHFNMIGN8BusFault in HardFault or NMI ignore
DIV_0_TRP4Divide by zero trap
UNALIGN_TRP3Unaligned trap
  • 0 Do not trap unaligned halfword and word accesses
  • 1 Trap unaligned halfword and word accesses
USERSETMPEND1User set main pending

SHPR1System Handler Priority Register 1

Address
0xE000ED18
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
PRI_623:16Priority of system handler 6, UsageFault
PRI_515:8Priority of system handler 5, BusFault
PRI_47:0Priority of system handler 4, MemManage
PRI_731:24Priority of system handler 7, SecureFault

SHPR2System Handler Priority Register 2

Address
0xE000ED1C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
PRI_1131:24Priority of system handler 11, SVCall

SHPR3System Handler Priority Register 3

Address
0xE000ED20
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
PRI_1423:16Priority of system handler 14, PendSV
PRI_127:0Priority of system handler 12, DebugMonitor
PRI_1531:24Priority of system handler 15, SysTick

SHCSRSystem Handler Control and State Register

Address
0xE000ED24
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
HARDFAULTPENDED21HardFault exception pended state
SVCALLPENDED15SVCall exception pended state
SYSTICKACT11SysTick exception active state
PENDSVACT10PendSV exception active state
SVCALLACT7SVCall exception active state
NMIACT5NMI exception active state
HARDFAULTACT2HardFault exception active state

CFSRConfigurable Fault Status Register

Address
0xE000ED28
Reset
0x00000000
Access
read/write
Size
32-bit
20 fields
FieldBitsWhat it does
DIVBYZERO25Divide by zero flag
UNALIGNED24Unaligned access flag
STKOF20Stack overflow flag
NOCP19No coprocessor flag
INVPC18Invalid PC flag
INVSTATE17Invalid state flag
UNDEFINSTR16Undefined instruction flag
BFARVALID15BFAR valid
LSPERR13Lazy state preservation error
STKERR12Stack error
UNSTKERR11Unstack error
IMPRECISERR10Imprecise error
PRECISERR9Precise error
IBUSERR8Instruction bus error
MMFARVALID7MMFAR valid flag
MLSPERR5MemManage lazy state preservation error flag
MSTKERR4MemManage stacking error flag
MUNSTKERR3MemManage unstacking error flag
DACCVIOL1Data access violation flag
IACCVIOL0Instruction access violation flag

HFSRHardFault Status Register

Address
0xE000ED2C
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
FORCED30Forced, configurable-priority exception escalated to HardFault
VECTTBL1Vector table read error
DEBUGEVT31Debug event

DFSRDebug Fault Status Register

Address
0xE000ED30
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
EXTERNAL4External event
VCATCH3Vector Catch event
DWTTRAP2Watchpoint event
BKPT1Breakpoint event
HALTED0Halt or step event

MMFARMemManage Fault Address Register

Address
0xE000ED34
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADDRESS31:0Data address for a MemManage fault

BFARBusFault Address Register

Address
0xE000ED38
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADDRESS31:0Data address for a precise BusFault

AFSRAuxiliary Fault Status Register

Address
0xE000ED3C
Reset
0x00000000
Access
read/write
Size
32-bit

ID_PFR0Processor Feature Register 0

Address
0xE000ED40
Reset
0x00000030
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
State17:4State one, T32 instruction set support
State03:0State two, A32 instruction set support

ID_PFR1Processor Feature Register 1

Address
0xE000ED44
Reset
0x00000200
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
MProgMod11:8M programmer's model
Security7:4Security Extension implemented

ID_DFR0Debug Feature Register 0

Address
0xE000ED48
Reset
0x00200000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
MProgDbg23:20M-profile debug

ID_AFR0Auxiliary Feature Register 0

Address
0xE000ED4C
Reset
0x00000000
Access
read only
Size
32-bit
4 fields
FieldBitsWhat it does
IMPDEF315:12Implementation defined feature 3
IMPDEF211:8Implementation defined feature 2
IMPDEF17:4Implementation defined feature 1
IMPDEF03:0Implementation defined feature 0

ID_MMFR0Memory Model Feature Register 0

Address
0xE000ED50
Reset
0x00000000
Access
read only
Size
32-bit
5 fields
FieldBitsWhat it does
AuxReg23:20Auxiliary Registers
TCM19:16Tightly Coupled Memories
ShareLvl15:12Shareability Levels
OuterShr11:8Outermost Shareability
PMSA7:4Protected Memory System Architecture

ID_MMFR1Memory Model Feature Register 1

Address
0xE000ED54
Reset
0x00000000
Access
read only
Size
32-bit

ID_MMFR2Memory Model Feature Register 2

Address
0xE000ED58
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
WFIStall27:24Wait For Interrupt stalling

ID_MMFR3Memory Model Feature Register 3

Address
0xE000ED5C
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
FieldBitsWhat it does
BPMaint11:8Branch predictor maintenance
CMaintSW7:4Cache maintenance set/way
CMaintVA3:0Cache maintenance by address

ID_ISAR0Instruction Set Attribute Register 0

Address
0xE000ED60
Reset
0x01101110
Access
read only
Size
32-bit
6 fields
FieldBitsWhat it does
Divide27:24Divide instructions
  • 1 SDIC and UDIV supported
Debug23:20Debug instructions
  • 1 BKPT supported
Coproc19:16Coprocessor instructions
  • 0 Only FPU coprocessor instructions
  • 1 Coprocessor instructions supported
CmpBranch15:12Compare and Branch instructions
  • 1 CBNZ and CBZ supported
BitField11:8Bit field instructions
  • 1 BFC, BFI, SBFX, and UBFX supported
BitCount7:4Bit count instructions
  • 1 CLZ supported

ID_ISAR1Instruction Set Attribute Register 1

Address
0xE000ED64
Reset
0x02211000
Access
read only
Size
32-bit
4 fields
FieldBitsWhat it does
Interwork27:24Interworking instructions
  • 2 BLX, BX, and loads to PC supported
Immediate23:20Data-processing instructions with long immediates
  • 2 ADDW, MOVW, MOVT, and SUBW supported
IfThen19:16If-Then instructions
  • 1 IT supported
Extend15:12Extend instructions
  • 1 SXTB, SXTH, UXTB, UXTH supported
  • 2 SXTB16, SXTAB, SXTAB16, SXTAH, UXTB16, iUXTAB, UXTAB16, and UXTAH supported

ID_ISAR2Instruction Set Attribute Register 2

Address
0xE000ED68
Reset
0x20112032
Access
read only
Size
32-bit
7 fields
FieldBitsWhat it does
MultU23:20Advanced unsigned Multiply instructions
  • 2 UMULL and UMLAL supported
MultS19:16Advanced signed Multiply instructions
  • 1 SMULL and SMLAL supported
  • 3 All saturating and DSP signed multiplies supported
Mult15:12Additional Multiply instructions
  • 2 MUL, MLA, and MLS supported
MultiAccessInt11:8Interruptible multi-access instructions
  • 0 LDM and STM are not interruptible
  • 1 LDM and STM are restartable
  • 2 LDM and STM are continuable
MemHint7:4Memory hint instructions
  • 3 PLI and PLD supported
LoadStore3:0Additional load/store instructions
  • 2 Load-acquire, store-release, and exclusive load and store supported
Reversal31:28Reversal instructions
  • 2 REV, REV16, REVSH, and RBIT supported

ID_ISAR3Instruction Set Attribute Register 3

Address
0xE000ED6C
Reset
0x01111110
Access
read only
Size
32-bit
7 fields
FieldBitsWhat it does
TrueNOP27:24True NOP instructions
  • 1 NOP instruction and compatible hints supported
T32Copy23:20T32 non flag-setting MOV instructions
  • 1 Encoding T1 of MOV (register) supports copying low register to low register
TabBranch19:16Table Branch instructions
  • 1 TBB and TBH supported
SynchPrim15:12Synchronization primitive instructions
  • 1 LDREX, STREX, LDREXB, STREXB, LDREXH, STREXH, and CLREX supported
SVC11:8Supervisor Call instructions
  • 1 SVC supported
SIMD7:4Single-instruction, multiple-data instructions
  • 1 SSAT, USAT, and Q-bit supported
  • 3 All packed arithmetic and GE-bits supported
Saturate3:0Saturating instructions
  • 0 No saturating instructions supported
  • 1 QADD, QDADD, QDSYB, QSUB and Q-bit supported

ID_ISAR4Instruction Set Attribute Register 4

Address
0xE000ED70
Reset
0x01310131
Access
read only
Size
32-bit
6 fields
FieldBitsWhat it does
PSR_M27:24M profile instructions to modify the Program Status Registers
  • 1 M profile forms of CPS, MRS, and MSR supported
SyncPrim_frac23:20Synchronization primitives fractional instructions
  • 3 LDREX, STREX, CLREX, LDREXB, LDREXH, STREXB, and STREXH supported
Barrier19:16Barrier instructions
  • 1 DMB, DSB, and ISB supported
Writeback11:8Writeback addressing modes
  • 1 All writeback addressing modes supported
WithShifts7:4Constant shifts instructions
  • 3 Constant shifts on load/store and other instructions supported
Unpriv3:0Unprivileged instructions
  • 2 LDRBT, LDRHT, LDRSBT, LDRSHT, LDRT, STRBT, STRHT, and STRT supported

ID_ISAR5Instruction Set Attribute Register 5

Address
0xE000ED74
Reset
0x00000000
Access
read only
Size
32-bit

CLIDRCache Level ID Register

Address
0xE000ED78
Reset
0x00000000
Access
read only
Size
32-bit
11 fields
FieldBitsWhat it does
LoUU29:27Level of Unification Uniprocessor
LoC26:24Level of Coherence
LoUIS23:21Level of Unification Inner Shareable
Ctype720:18Cache type at level 7
  • 0 No cache
  • 1 Instruction cache only
  • 2 Data cache only
  • 3 Separate instruction and data caches
  • 4 Unified cache
Ctype617:15Cache type at level 6
  • 0 No cache
  • 1 Instruction cache only
  • 2 Data cache only
  • 3 Separate instruction and data caches
  • 4 Unified cache
Ctype514:12Cache type at level 5
  • 0 No cache
  • 1 Instruction cache only
  • 2 Data cache only
  • 3 Separate instruction and data caches
  • 4 Unified cache
Ctype411:9Cache type at level 4
  • 0 No cache
  • 1 Instruction cache only
  • 2 Data cache only
  • 3 Separate instruction and data caches
  • 4 Unified cache
Ctype38:6Cache type at level 3
  • 0 No cache
  • 1 Instruction cache only
  • 2 Data cache only
  • 3 Separate instruction and data caches
  • 4 Unified cache
Ctype25:3Cache type at level 2
  • 0 No cache
  • 1 Instruction cache only
  • 2 Data cache only
  • 3 Separate instruction and data caches
  • 4 Unified cache
Ctype12:0Cache type at level 1
  • 0 No cache
  • 1 Instruction cache only
  • 2 Data cache only
  • 3 Separate instruction and data caches
  • 4 Unified cache
ICB31:30Inner cache boundary
  • 0 Not disclosed in this mechanism
  • 1 L1 cache is the highest inner level
  • 2 L2 cache is the highest inner level
  • 3 L3 cache is the highest inner level

CTRCache Type Register

Address
0xE000ED7C
Reset
0x00000000
Access
read only
Size
32-bit
5 fields
FieldBitsWhat it does
CWG27:24Cache Write-back Granule
ERG23:20Exclusives Reservation Granule
DminLine19:16Data cache minimum line length
IminLine3:0Instruction cache minimum line length
Format31:29Cache Type Register format
  • 0 No cache type information provided
  • 4 Cache type information is provided

CCSIDRCurrent Cache Size ID register

Address
0xE000ED80
Reset
0x00000000
Access
read only
Size
32-bit
7 fields
FieldBitsWhat it does
WB30Write-Back
RA29Read-Allocate
WA28Write-Allocate
NumSets27:13Number of sets - 1
Associativity12:3Associativity - 1
LineSize2:0log2(number of words per line) - 2
WT31Write-Through

CSSELRCache Size Selection Register

Address
0xE000ED84
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
Level3:1Cache level - 1
InD0Instruction not Data

CPACRCoprocessor Access Control Register

Address
0xE000ED88
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
FieldBitsWhat it does
CP1123:22CP11 Privilege
CP1021:20Floating-point Extension access rights
CP715:14Coprocessor 7 privilege
CP613:12Coprocessor 6 privilege
CP511:10Coprocessor 5 privilege
CP49:8Coprocessor 4 privilege
CP37:6Coprocessor 3 privilege
CP25:4Coprocessor 2 privilege
CP13:2Coprocessor 1 privilege
CP01:0Coprocessor 0 privilege

NSACRNon-secure Access Control Register

Address
0xE000ED8C
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
FieldBitsWhat it does
CP1111CP11 Non-secure
CP1010Floating-point Extension Non-secure
CP77Coprocessor 7 Non-secure
CP66Coprocessor 6 Non-secure
CP55Coprocessor 5 Non-secure
CP44Coprocessor 4 Non-secure
CP33Coprocessor 3 Non-secure
CP22Coprocessor 2 Non-secure
CP11Coprocessor 1 Non-secure
CP00Coprocessor 0 Non-secure