PIC32CK1012SG00100 MCLK registers The 13 registers of MCLK (Main Clock), from 0x44012000, with their reset value and every field. The PIC32CK1012SG00100 has 5596 registers in 69 peripherals, one page each.
MCLK Main Clock INTENCLRInterrupt Enable Clear
Address 0x44012000
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CKRDY 0 Clock Ready Interrupt Enable
INTENSETInterrupt Enable Set
Address 0x44012004
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does CKRDY 0 Clock Ready Interrupt Enable
INTFLAGInterrupt Flag Status and Clear
Address 0x44012008
Reset 0x00000001
Access read/write
Size 32-bit 1 field
Field Bits What it does CKRDY 0 Clock Ready
CLKDIVClock Divider Control
Address 0x4401200C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DIV 7:0 Clock Domain Division Factor1 Divide by 12 Divide by 24 Divide by 48 Divide by 816 Divide by 1632 Divide by 3264 Divide by 64128 Divide by 128
CLKMSK0Peripheral Clock Enable Mask
Address 0x4401203C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does MASK 31:0 Peripheral Clock Enable Mask
CLKMSK1Peripheral Clock Enable Mask
Address 0x44012040
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does MASK 31:0 Peripheral Clock Enable Mask
CLKMSK2Peripheral Clock Enable Mask
Address 0x44012044
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does MASK 31:0 Peripheral Clock Enable Mask
CLKMSK3Peripheral Clock Enable Mask
Address 0x44012048
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does MASK 31:0 Peripheral Clock Enable Mask
CLKMSK4Peripheral Clock Enable Mask
Address 0x4401204C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does MASK 31:0 Peripheral Clock Enable Mask
CLKMSK5Peripheral Clock Enable Mask
Address 0x44012050
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does MASK 31:0 Peripheral Clock Enable Mask
CLKMSK6Peripheral Clock Enable Mask
Address 0x44012054
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does MASK 31:0 Peripheral Clock Enable Mask
CLKMSK7Peripheral Clock Enable Mask
Address 0x44012058
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does MASK 31:0 Peripheral Clock Enable Mask
CLKMSK8Peripheral Clock Enable Mask
Address 0x4401205C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does MASK 31:0 Peripheral Clock Enable Mask
BETA