The 32 registers of TCC1 (Timer Counter for Control Applications), from 0x4481A000, with their reset value and every field. The PIC32CK1012SG01048 has 5758 registers in 71 peripherals, one page each.
TCC1 Timer Counter for Control Applications
CTRLAControl A
Address
0x4481A000
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
CPTEN5
29
Capture Channel 5 Enable
CPTEN4
28
Capture Channel 4 Enable
CPTEN3
27
Capture Channel 3 Enable
CPTEN2
26
Capture Channel 2 Enable
CPTEN1
25
Capture Channel 1 Enable
CPTEN0
24
Capture Channel 0 Enable
DMAOS
23
DMA One-shot Trigger Mode
FCYCLE
16
Full Cycle
MSYNC
15
Master Synchronization (only for TCC Slave Instance)
ALOCK
14
Auto Lock
PRESCSYNC
13:12
Prescaler and Counter Synchronization Selection
0 Reload or reset counter on next GCLK
1 Reload or reset counter on next prescaler clock
2 Reload or reset counter on next GCLK and reset prescaler counter
RUNSTDBY
11
Run in Standby
PRESCALER
10:8
Prescaler
0 No division
1 Divide by 2
2 Divide by 4
3 Divide by 8
4 Divide by 16
5 Divide by 64
6 Divide by 256
7 Divide by 1024
RESOLUTION
6:5
Enhanced Resolution
0 Dithering is disabled
1 Dithering is done every 16 PWM frames
2 Dithering is done every 32 PWM frames
3 Dithering is done every 64 PWM frames
ENABLE
1
Enable
SWRST
0
Software Reset
CTRLBCLRControl B Clear
Address
0x4481A004
Reset
0x00
Access
read/write
7CMD2
6CMD1
5CMD0
4IDXCMD1
3IDXCMD0
2ONESHOT
1LUPD
0DIR
5 fields
Field
Bits
What it does
CMD
7:5
TCC Command
0 No action
1 Clear start, restart or retrigger
2 Force stop
3 Force update or double buffered registers
4 Force COUNT read synchronization
5 One-shot DMA trigger
IDXCMD
4:3
Ramp Index Command
0 Command disabled: Index toggles between cycles A and B
1 Set index: cycle B will be forced in the next cycle
2 Clear index: cycle A will be forced in the next cycle
3 Hold index: the next cycle will be the same as the current cycle
ONESHOT
2
One-Shot
LUPD
1
Lock Update
DIR
0
Counter Direction
CTRLBSETControl B Set
Address
0x4481A005
Reset
0x00
Access
read/write
7CMD2
6CMD1
5CMD0
4IDXCMD1
3IDXCMD0
2ONESHOT
1LUPD
0DIR
5 fields
Field
Bits
What it does
CMD
7:5
TCC Command
0 No action
1 Clear start, restart or retrigger
2 Force stop
3 Force update or double buffered registers
4 Force COUNT read synchronization
5 One-shot DMA trigger
IDXCMD
4:3
Ramp Index Command
0 Command disabled: Index toggles between cycles A and B
1 Set index: cycle B will be forced in the next cycle
2 Clear index: cycle A will be forced in the next cycle
3 Hold index: the next cycle will be the same as the current cycle
ONESHOT
2
One-Shot
LUPD
1
Lock Update
DIR
0
Counter Direction
SYNCBUSYSynchronization Busy
Address
0x4481A008
Reset
0x00000000
Access
read only
Size
32-bit
14 fields
Field
Bits
What it does
CC5
13
Compare Channel 5 Busy
CC4
12
Compare Channel 4 Busy
CC3
11
Compare Channel 3 Busy
CC2
10
Compare Channel 2 Busy
CC1
9
Compare Channel 1 Busy
CC0
8
Compare Channel 0 Busy
PER
7
Period Busy
WAVE
6
Wave Busy
PATT
5
Pattern Busy
COUNT
4
Count Busy
STATUS
3
Status Busy
CTRLB
2
Ctrlb Busy
ENABLE
1
Enable Busy
SWRST
0
Swrst Busy
FCTRLARecoverable Fault A Configuration
Address
0x4481A00C
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FILTERVAL
27:24
Fault A Filter Value
BLANKVAL
23:16
Fault A Blanking Time
BLANKPRESC
15
Fault A Blanking Prescaler
CAPTURE
14:12
Fault A Capture Action
0 No capture
1 Capture on fault
2 Minimum capture
3 Maximum capture
4 Minimum local detection
5 Maximum local detection
6 Minimum and maximum local detection
7 Capture with ramp index as MSB value
CHSEL
11:10
Fault A Capture Channel
0 Capture value stored in channel 0
1 Capture value stored in channel 1
2 Capture value stored in channel 2
3 Capture value stored in channel 3
HALT
9:8
Fault A Halt Mode
0 Halt action disabled
1 Hardware halt action
2 Software halt action
3 Non-recoverable fault
RESTART
7
Fault A Restart
BLANK
6:5
Fault A Blanking Mode
0 Blanking applied from start of the ramp
1 Blanking applied from rising edge of the output waveform
2 Blanking applied from falling edge of the output waveform
3 Blanking applied from each toggle of the output waveform
QUAL
4
Fault A Qualification
KEEP
3
Fault A Keeper
SRC
1:0
Fault A Source
0 Fault input disabled
1 MCEx (x=0,1) event input
2 Inverted MCEx (x=0,1) event input
3 Alternate fault (A or B) state at the end of the previous period
FCTRLBRecoverable Fault B Configuration
Address
0x4481A010
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FILTERVAL
27:24
Fault B Filter Value
BLANKVAL
23:16
Fault B Blanking Time
BLANKPRESC
15
Fault B Blanking Prescaler
CAPTURE
14:12
Fault B Capture Action
0 No capture
1 Capture on fault
2 Minimum capture
3 Maximum capture
4 Minimum local detection
5 Maximum local detection
6 Minimum and maximum local detection
7 Capture with ramp index as MSB value
CHSEL
11:10
Fault B Capture Channel
0 Capture value stored in channel 0
1 Capture value stored in channel 1
2 Capture value stored in channel 2
3 Capture value stored in channel 3
HALT
9:8
Fault B Halt Mode
0 Halt action disabled
1 Hardware halt action
2 Software halt action
3 Non-recoverable fault
RESTART
7
Fault B Restart
BLANK
6:5
Fault B Blanking Mode
0 Blanking applied from start of the ramp
1 Blanking applied from rising edge of the output waveform
2 Blanking applied from falling edge of the output waveform
3 Blanking applied from each toggle of the output waveform
QUAL
4
Fault B Qualification
KEEP
3
Fault B Keeper
SRC
1:0
Fault B Source
0 Fault input disabled
1 MCEx (x=0,1) event input
2 Inverted MCEx (x=0,1) event input
3 Alternate fault (A or B) state at the end of the previous period
WEXCTRLWaveform Extension Configuration
Address
0x4481A014
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
DTLS
23:16
Dead-time Low Side Outputs Value
DTIEN3
11
Dead-time Insertion Generator 3 Enable
DTIEN2
10
Dead-time Insertion Generator 2 Enable
DTIEN1
9
Dead-time Insertion Generator 1 Enable
DTIEN0
8
Dead-time Insertion Generator 0 Enable
OTMX
1:0
Output Matrix
DTHS
31:24
Dead-time High Side Outputs Value
DRVCTRLDriver Control
Address
0x4481A018
Reset
0x00000000
Access
read/write
Size
32-bit
26 fields
Field
Bits
What it does
FILTERVAL0
27:24
Non-Recoverable Fault Input 0 Filter Value
INVEN7
23
Output Waveform 7 Inversion
INVEN6
22
Output Waveform 6 Inversion
INVEN5
21
Output Waveform 5 Inversion
INVEN4
20
Output Waveform 4 Inversion
INVEN3
19
Output Waveform 3 Inversion
INVEN2
18
Output Waveform 2 Inversion
INVEN1
17
Output Waveform 1 Inversion
INVEN0
16
Output Waveform 0 Inversion
NRV7
15
Non-Recoverable State 7 Output Value
NRV6
14
Non-Recoverable State 6 Output Value
NRV5
13
Non-Recoverable State 5 Output Value
NRV4
12
Non-Recoverable State 4 Output Value
NRV3
11
Non-Recoverable State 3 Output Value
NRV2
10
Non-Recoverable State 2 Output Value
NRV1
9
Non-Recoverable State 1 Output Value
NRV0
8
Non-Recoverable State 0 Output Value
NRE7
7
Non-Recoverable State 7 Output Enable
NRE6
6
Non-Recoverable State 6 Output Enable
NRE5
5
Non-Recoverable State 5 Output Enable
NRE4
4
Non-Recoverable State 4 Output Enable
NRE3
3
Non-Recoverable State 3 Output Enable
NRE2
2
Non-Recoverable State 2 Output Enable
NRE1
1
Non-Recoverable State 1 Output Enable
NRE0
0
Non-Recoverable State 0 Output Enable
FILTERVAL1
31:28
Non-Recoverable Fault Input 1 Filter Value
DBGCTRLDebug Control
Address
0x4481A01E
Reset
0x00
Access
read/write
7–
6–
5–
4–
3–
2FDDBD
1–
0DBGRUN
2 fields
Field
Bits
What it does
FDDBD
2
Fault Detection on Debug Break Detection
DBGRUN
0
Debug Running Mode
EVCTRLEvent Control
Address
0x4481A020
Reset
0x00000000
Access
read/write
Size
32-bit
22 fields
Field
Bits
What it does
MCEO5
29
Match or Capture Channel 5 Event Output Enable
MCEO4
28
Match or Capture Channel 4 Event Output Enable
MCEO3
27
Match or Capture Channel 3 Event Output Enable
MCEO2
26
Match or Capture Channel 2 Event Output Enable
MCEO1
25
Match or Capture Channel 1 Event Output Enable
MCEO0
24
Match or Capture Channel 0 Event Output Enable
MCEI5
21
Match or Capture Channel 5 Event Input Enable
MCEI4
20
Match or Capture Channel 4 Event Input Enable
MCEI3
19
Match or Capture Channel 3 Event Input Enable
MCEI2
18
Match or Capture Channel 2 Event Input Enable
MCEI1
17
Match or Capture Channel 1 Event Input Enable
MCEI0
16
Match or Capture Channel 0 Event Input Enable
TCEI1
15
Timer/counter Event 1 Input Enable
TCEI0
14
Timer/counter Event 0 Input Enable
TCINV1
13
Inverted Event 1 Input Enable
TCINV0
12
Inverted Event 0 Input Enable
CNTEO
10
Timer/counter Output Event Enable
TRGEO
9
Retrigger Output Event Enable
OVFEO
8
Overflow/Underflow Output Event Enable
CNTSEL
7:6
Timer/counter Output Event Mode
0 An interrupt/event is generated when a new counter cycle starts
1 An interrupt/event is generated when a counter cycle ends
3 An interrupt/event is generated when a new counter cycle starts or a counter cycle ends
EVACT1
5:3
Timer/counter Input Event1 Action
0 Event action disabled
1 Re-trigger counter on event
2 Direction control
3 Stop counter on event
4 Decrement counter on event
6 Period capture value in CC1 register, pulse width capture value in CC0 register
7 Non-recoverable fault
EVACT0
2:0
Timer/counter Input Event0 Action
0 Event action disabled
1 Start, restart or re-trigger counter on event
2 Count on event
3 Start counter on event
4 Increment counter on event
5 Count on active state of asynchronous event
6 Stamp capture
7 Non-recoverable fault
INTENCLRInterrupt Enable Clear
Address
0x4481A024
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
MC5
21
Match or Capture Channel 5 Interrupt Enable
MC4
20
Match or Capture Channel 4 Interrupt Enable
MC3
19
Match or Capture Channel 3 Interrupt Enable
MC2
18
Match or Capture Channel 2 Interrupt Enable
MC1
17
Match or Capture Channel 1 Interrupt Enable
MC0
16
Match or Capture Channel 0 Interrupt Enable
FAULT1
15
Non-Recoverable Fault 1 Interrupt Enable
FAULT0
14
Non-Recoverable Fault 0 Interrupt Enable
FAULTB
13
Recoverable Fault B Interrupt Enable
FAULTA
12
Recoverable Fault A Interrupt Enable
DFS
11
Non-Recoverable Debug Fault Interrupt Enable
UFS
10
Non-Recoverable Update Fault Interrupt Enable
ERR
3
Error Interrupt Enable
CNT
2
Counter Interrupt Enable
TRG
1
Retrigger Interrupt Enable
OVF
0
Overflow Interrupt Enable
INTENSETInterrupt Enable Set
Address
0x4481A028
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
MC5
21
Match or Capture Channel 5 Interrupt Enable
MC4
20
Match or Capture Channel 4 Interrupt Enable
MC3
19
Match or Capture Channel 3 Interrupt Enable
MC2
18
Match or Capture Channel 2 Interrupt Enable
MC1
17
Match or Capture Channel 1 Interrupt Enable
MC0
16
Match or Capture Channel 0 Interrupt Enable
FAULT1
15
Non-Recoverable Fault 1 Interrupt Enable
FAULT0
14
Non-Recoverable Fault 0 Interrupt Enable
FAULTB
13
Recoverable Fault B Interrupt Enable
FAULTA
12
Recoverable Fault A Interrupt Enable
DFS
11
Non-Recoverable Debug Fault Interrupt Enable
UFS
10
Non-Recoverable Update Fault Interrupt Enable
ERR
3
Error Interrupt Enable
CNT
2
Counter Interrupt Enable
TRG
1
Retrigger Interrupt Enable
OVF
0
Overflow Interrupt Enable
INTFLAGInterrupt Flag Status and Clear
Address
0x4481A02C
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
MC5
21
Match or Capture 5
MC4
20
Match or Capture 4
MC3
19
Match or Capture 3
MC2
18
Match or Capture 2
MC1
17
Match or Capture 1
MC0
16
Match or Capture 0
FAULT1
15
Non-Recoverable Fault 1
FAULT0
14
Non-Recoverable Fault 0
FAULTB
13
Recoverable Fault B
FAULTA
12
Recoverable Fault A
DFS
11
Non-Recoverable Debug Fault
UFS
10
Non-Recoverable Update Fault
ERR
3
Error
CNT
2
Counter
TRG
1
Retrigger
OVF
0
Overflow
STATUSStatus
Address
0x4481A030
Reset
0x00000001
Access
read/write
Size
32-bit
27 fields
Field
Bits
What it does
CMP5
29
Compare Channel 5 Value
CMP4
28
Compare Channel 4 Value
CMP3
27
Compare Channel 3 Value
CMP2
26
Compare Channel 2 Value
CMP1
25
Compare Channel 1 Value
CMP0
24
Compare Channel 0 Value
CCBUFV5
21
Compare Channel 5 Buffer Valid
CCBUFV4
20
Compare Channel 4 Buffer Valid
CCBUFV3
19
Compare Channel 3 Buffer Valid
CCBUFV2
18
Compare Channel 2 Buffer Valid
CCBUFV1
17
Compare Channel 1 Buffer Valid
CCBUFV0
16
Compare Channel 0 Buffer Valid
FAULT1
15
Non-Recoverable Fault 1 State
FAULT0
14
Non-Recoverable Fault 0 State
FAULTB
13
Recoverable Fault B State
FAULTA
12
Recoverable Fault A State
FAULT1IN
11
Non-Recoverable Fault1 Input
FAULT0IN
10
Non-Recoverable Fault0 Input
FAULTBIN
9
Recoverable Fault B Input
FAULTAIN
8
Recoverable Fault A Input
PERBUFV
7
Period Buffer Valid
PATTBUFV
5
Pattern Buffer Valid
SLAVE
4
Slave
DFS
3
Non-Recoverable Debug Fault State
UFS
2
Non-recoverable Update Fault State
IDX
1
Ramp
STOP
0
Stop
COUNTCount
Address
0x4481A034
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
COUNT
31:0
Counter Value
COUNT
31:4
Counter Value
COUNT
31:5
Counter Value
COUNT
31:6
Counter Value
PATTPattern
Address
0x4481A038
Reset
0x0000
Access
read/write
Size
16-bit
16 fields
Field
Bits
What it does
PGV7
15
Pattern Generator 7 Output Value
PGV6
14
Pattern Generator 6 Output Value
PGV5
13
Pattern Generator 5 Output Value
PGV4
12
Pattern Generator 4 Output Value
PGV3
11
Pattern Generator 3 Output Value
PGV2
10
Pattern Generator 2 Output Value
PGV1
9
Pattern Generator 1 Output Value
PGV0
8
Pattern Generator 0 Output Value
PGE7
7
Pattern Generator 7 Output Enable
PGE6
6
Pattern Generator 6 Output Enable
PGE5
5
Pattern Generator 5 Output Enable
PGE4
4
Pattern Generator 4 Output Enable
PGE3
3
Pattern Generator 3 Output Enable
PGE2
2
Pattern Generator 2 Output Enable
PGE1
1
Pattern Generator 1 Output Enable
PGE0
0
Pattern Generator 0 Output Enable
WAVEWaveform Control
Address
0x4481A03C
Reset
0x00000000
Access
read/write
Size
32-bit
17 fields
Field
Bits
What it does
SWAP3
27
Swap DTI Output Pair 3
SWAP2
26
Swap DTI Output Pair 2
SWAP1
25
Swap DTI Output Pair 1
SWAP0
24
Swap DTI Output Pair 0
POL5
21
Channel 5 Polarity
POL4
20
Channel 4 Polarity
POL3
19
Channel 3 Polarity
POL2
18
Channel 2 Polarity
POL1
17
Channel 1 Polarity
POL0
16
Channel 0 Polarity
CICCEN3
11
Circular Channel 3 Enable
CICCEN2
10
Circular Channel 2 Enable
CICCEN1
9
Circular Channel 1 Enable
CICCEN0
8
Circular Channel 0 Enable
CIPEREN
7
Circular period Enable
RAMP
6:4
Ramp Mode
0 RAMP1 operation
1 Alternative RAMP2 operation
2 RAMP2 operation
3 Critical RAMP2 operation
4 Critical Swapped RAMP2 operation
WAVEGEN
2:0
Waveform Generation
0 Normal frequency
1 Match frequency
2 Normal PWM
3 Dual compare PWM
4 Dual-slope critical
5 Dual-slope with interrupt/event condition when COUNT reaches ZERO
6 Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP
7 Dual-slope with interrupt/event condition when COUNT reaches TOP
BETA