PIC32CK1012SG01100 CMCC registers The 11 registers of CMCC (Cortex M Cache Controller), from 0x44808000, with their reset value and every field. The PIC32CK1012SG01100 has 5758 registers in 71 peripherals, one page each.
CMCC Cortex M Cache Controller TYPECache Type Register
Address 0x44808000
Reset 0x000012D2
Access read only
Size 32-bit 6 fields
Field Bits What it does CLSIZE 13:11 Cache Line Size2 Cache Line Size is 16 bytes CSIZE 10:8 Cache Size0 Cache Size is 1 KB1 Cache Size is 2 KB2 Cache Size is 4 KB LCKDOWN 7 Lock Down supported WAYNUM 6:5 Number of Way0 Direct Mapped Cache1 2-WAY set associative2 4-WAY set associative RRP 4 Round Robin Policy supported GCLK 1 dynamic Clock Gating supported
CFGCache Configuration Register
Address 0x44808004
Reset 0x00000020
Access read/write
Size 32-bit 3 fields
Field Bits What it does CSIZESW 6:4 Cache size configured by software0 The Cache Size is configured to 1KB1 The Cache Size is configured to 2KB2 The Cache Size is configured to 4KB DCDIS 2 Data Cache Disable ICDIS 1 Instruction Cache Disable
CTRLCache Control Register
Address 0x44808008
Reset 0x00000000
Access write only
Size 32-bit 1 field
Field Bits What it does CEN 0 Cache Controller Enable
SRCache Status Register
Address 0x4480800C
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does CSTS 0 Cache Controller Status
LCKWAYCache Lock per Way Register
Address 0x44808010
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does LCKWAY 3:0 Lockdown way Register
MAINT0Cache Maintenance Register 0
Address 0x44808020
Reset 0x00000000
Access write only
Size 32-bit 1 field
Field Bits What it does INVALL 0 Cache Controller invalidate All
MAINT1Cache Maintenance Register 1
Address 0x44808024
Reset 0x00000000
Access write only
Size 32-bit 2 fields
Field Bits What it does INDEX 11:4 Invalidate Index WAY 31:28 Invalidate Way1 Way 0 is selection for index invalidation2 Way 1 is selection for index invalidation4 Way 2 is selection for index invalidation8 Way 3 is selection for index invalidation
MCFGCache Monitor Configuration Register
Address 0x44808028
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does MODE 1:0 Cache Controller Monitor Counter Mode0 Cycle counter1 Instruction hit counter2 Data hit counter
MENCache Monitor Enable Register
Address 0x4480802C
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does MENABLE 0 Cache Controller Monitor Enable
MCTRLCache Monitor Control Register
Address 0x44808030
Reset 0x00000000
Access write only
Size 32-bit 1 field
Field Bits What it does SWRST 0 Cache Controller Software Reset
MSRCache Monitor Status Register
Address 0x44808034
Reset 0x00000000
Access read only
Size 32-bit 1 field
Field Bits What it does EVENT_CNT 31:0 Monitor Event Counter
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