The 37 registers of DSU (Device Service Unit), from 0x44000000, with their reset value and every field. The PIC32CK1012SG01100 has 5758 registers in 71 peripherals, one page each.
DSU Device Service Unit
CTRLControl
Address
0x44000000
Reset
0x00000000
Access
write only
Size
32-bit
2 fields
Field
Bits
What it does
SWRST
0
Software Reset
CMD
31:16
Command Register
0 No operation
42240 32-bit Cyclic Redundancy Code
42241 Global Memory built-in self-test
42242 Memory Set
ADDRAddress
Address
0x44000004
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
AMOD
1:0
Access Mode
0 STATUSA.FAIL rises upon first error and algorithm stops (STATUSA.DONE rises).
1 STATUSA.FAIL rises when an error is detected and algorith stops until STATUSA.FAIL is cleared. Once cleared, the algorithm is resumed going to next test step.
ADDR
31:2
Address
LENGTHLength
Address
0x44000008
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
LENGTH
31:2
Length
DATAData
Address
0x4400000C
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
INDEX
12:8
MBIST bit Index
STATE
4:0
MBIST state
9 SET1 Phase: read '0' write '1'
10 SET2 Phase: read '1' write '0'
11 SET2B Phase: read '0' write '1'
12 CLEAR1 Phase: read '1' write '0'
13 CLEAR2 Phase: read '0' write '1'
14 CLEAR2B Phase: read '1' write '0'
15 READ Phase: check memory is cleared
DATA
31:0
Data
CFGConfiguration
Address
0x44000010
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
MBFI
2
Enables the Memory Bist Fault Injection
DCCDMALEVEL1
1
DMA Trigger 1 Level
0 Trigger x rises when DCC is read and falls when it is written
1 Trigger x rises when DCC is written and falls when it is read
DCCDMALEVEL0
0
DMA Trigger 0 Level
0 Trigger x rises when DCC is read and falls when it is written
1 Trigger x rises when DCC is written and falls when it is read
MISC
31:8
Device Specific Configuration Register
MBFI0Memory Bist Fault Injection 0
Address
0x44000014
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
FTYPE
7
Fault type
0 Stuck At 0
1 Stuck At 1
AMMOD
6
Address matching mode
0 Address match, fault injected when the masked master address matches with the masked bcc1.addr
1 Always matches, fault injected every AHB access
BIDX
4:0
Bit Index of injected fault
AMMSK
31:8
Address matching Mask (Word address)
MBFI1Memory Bist Fault Injection 1
Address
0x44000018
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
ADDR
31:2
Word Address
STATUSAStatus A
Address
0x44000100
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
BREXT1
17
BootRom 1 Phase Extension
BREXT0
16
BootRom 0 Phase Extension
CRSTEXT1
9
CPU 1 Reset Phase Extension
CRSTEXT0
8
CPU 0 Reset Phase Extension
PERR
3
Protection Error
BERR
2
Bus Error
FAIL
1
Failure
DONE
0
Done
STATUSBStatus B
Address
0x44000104
Reset
0x00000000
Access
read only
Size
32-bit
6 fields
Field
Bits
What it does
HPE
10
Hot-Plugging Enable
DBGPRES
8
Debugger Present
DCCD1
3
Debug Communication Channel 1 Dirty
DCCD0
2
Debug Communication Channel 0 Dirty
BCCD1
1
Boot ROM Communication Channel 1 Dirty
BCCD0
0
Boot ROM Communication Channel 0 Dirty
STATUSCStatus C
Address
0x44000108
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
INDEX
12:8
MBIST, MSA, PMSA bit Index
STATE
4:0
Core State
0 State Machine Ready
1 CRC32 Operation Ongoing
4 Memory Set
8 MBIST fill memory with zeroes
9 SET1 Phase: read '0' write '1'
10 SET2 Phase: read '1' write '0'
11 SET2B Phase: read '0' write '1'
12 CLEAR1 Phase: read '1' write '0'
13 CLEAR2 Phase: read '0' write '1'
14 CLEAR2B Phase: read '1' write '0'
15 READ Phase: check memory is cleared
BCC0Boot ROM Communication Channel x
Address
0x44000110
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DATA
31:0
Data
BCC1Boot ROM Communication Channel x
Address
0x44000114
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DATA
31:0
Data
DCC0Debug Communication Channel x
Address
0x44000118
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DATA
31:0
Data
DCC1Debug Communication Channel x
Address
0x4400011C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DATA
31:0
Data
DIDDevice Identification
Address
0x44000120
Reset
0x19585053
Access
read only
Size
32-bit
5 fields
Field
Bits
What it does
PRODUCT
27:20
Product
DEVSEL
19:12
Device Select
MANID
11:1
Manufacturer ID
MARKER
0
Marker Bit
REVISION
31:28
Revision
DALDebugger Access Level
Address
0x44000124
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
CPU1
3:2
Per CPU Debugger Access Level
0 Debugger targeting CPU0 domain can only access the DSU external address space otherwise debugger access is disabled
1 Debugger can access only non-secure regions
2 Debugger can access secure and non-secure regions
3 No CPU in this slot
CPU0
1:0
Per CPU Debugger Access Level
0 Debugger targeting CPU0 domain can only access the DSU external address space otherwise debugger access is disabled
1 Debugger can access only non-secure regions
2 Debugger can access secure and non-secure regions
3 No CPU in this slot
ENTRY0Coresight ROM Table Entry x
Address
0x44001000
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
FMT
1
Format
EPRES
0
Entry Present
ADDOFF
31:12
Address Offset
ENTRY1Coresight ROM Table Entry x
Address
0x44001004
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
FMT
1
Format
EPRES
0
Entry Present
ADDOFF
31:12
Address Offset
ENTRY2Coresight ROM Table Entry x
Address
0x44001008
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
FMT
1
Format
EPRES
0
Entry Present
ADDOFF
31:12
Address Offset
ENTRY3Coresight ROM Table Entry x
Address
0x4400100C
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
FMT
1
Format
EPRES
0
Entry Present
ADDOFF
31:12
Address Offset
ENTRY4Coresight ROM Table Entry x
Address
0x44001010
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
FMT
1
Format
EPRES
0
Entry Present
ADDOFF
31:12
Address Offset
ENTRY5Coresight ROM Table Entry x
Address
0x44001014
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
FMT
1
Format
EPRES
0
Entry Present
ADDOFF
31:12
Address Offset
ENTRY6Coresight ROM Table Entry x
Address
0x44001018
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
FMT
1
Format
EPRES
0
Entry Present
ADDOFF
31:12
Address Offset
ENTRY7Coresight ROM Table Entry x
Address
0x4400101C
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
FMT
1
Format
EPRES
0
Entry Present
ADDOFF
31:12
Address Offset
MEMTYPECoresight ROM Table Memory Type
Address
0x44001FCC
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
SMEMP
0
System Memory Present
PID4Coresight ROM Table Peripheral Identification 4
Address
0x44001FD0
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
FKBC
7:4
4KB count
JEPCC
3:0
JEP-106 Continuation Code
PID5Coresight ROM Table Peripheral Identification 5
Address
0x44001FD4
Reset
0x00000000
Access
read only
Size
32-bit
PID6Coresight ROM Table Peripheral Identification 6
Address
0x44001FD8
Reset
0x00000000
Access
read only
Size
32-bit
PID7Coresight ROM Table Peripheral Identification 7
Address
0x44001FDC
Reset
0x00000000
Access
read only
Size
32-bit
PID0Coresight ROM Table Peripheral Identification 0
Address
0x44001FE0
Reset
0x000000D0
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
PARTNBL
7:0
Part Number Low
PID1Coresight ROM Table Peripheral Identification 1
Address
0x44001FE4
Reset
0x0000009C
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
JEPIDCL
7:4
Low part of the JEP-106 Identity Code
PARTNBH
3:0
Part Number High
PID2Coresight ROM Table Peripheral Identification 2
Address
0x44001FE8
Reset
0x0000002A
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
REVISION
7:4
Revision Number
JEPU
3
JEP-106 Identity Code is used
JEPIDCH
2:0
JEP-106 Identity Code High
PID3Coresight ROM Table Peripheral Identification 3
Address
0x44001FEC
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
REVAND
7:4
Revision Number
CUSMOD
3:0
ARM CUSMOD
CID0Coresight ROM Table Component Identification 0
Address
0x44001FF0
Reset
0x0000000D
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
PREAMBLEB0
7:0
Preamble Byte 0
CID1Coresight ROM Table Component Identification 1
Address
0x44001FF4
Reset
0x00000010
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
CCLASS
7:4
Component Class
PREAMBLE
3:0
Preamble
CID2Coresight ROM Table Component Identification 2
Address
0x44001FF8
Reset
0x00000005
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
PREAMBLEB2
7:0
Preamble Byte 2
CID3Coresight ROM Table Component Identification 3
BETA