PIC32CK1025SG01100 EBI registers

The 18 registers of EBI (External Bus Interface), from 0x4502C000, with their reset value and every field. The PIC32CK1025SG01100 has 6232 registers in 78 peripherals, one page each.

EBI External Bus Interface

CS_X0.SMC_SETUPSMC Setup Register

Address
0x4502C000
Reset
0x01010101
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_SETUP29:24NCS Setup Length in READ Access
NRD_SETUP21:16NRD Setup Length
NCS_WR_SETUP13:8NCS Setup Length in WRITE Access
NWE_SETUP5:0NWE Setup Length

CS_X0.SMC_PULSESMC Pulse Register

Address
0x4502C004
Reset
0x01010101
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_PULSE30:24NCS Pulse Length in READ Access
NRD_PULSE22:16NRD Pulse Length
NCS_WR_PULSE14:8NCS Pulse Length in WRITE Access
NWE_PULSE6:0NWE Pulse Length

CS_X0.SMC_CYCLESMC Cycle Register

Address
0x4502C008
Reset
0x00030003
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
NRD_CYCLE24:16Total Read Cycle Length
NWE_CYCLE8:0Total Write Cycle Length

CS_X0.SMC_MODESMC Mode Register

Address
0x4502C00C
Reset
0x10001003
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
PS29:28Page Size
  • 0 4-byte page
  • 1 8-byte page
  • 2 16-byte page
  • 3 32-byte page
PMEN24Page Mode Enabled
TDF_MODE20TDF Optimization
TDF_CYCLES19:16Data Float Time
DBW12Data Bus Width
  • 0 8-bit Data Bus
  • 1 16-bit Data Bus
BAT8Byte Access Type
  • 0 Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1.
  • 1 Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD.
EXNW_MODE5:4NWAIT Mode
  • 0 Disabled-The NWAIT input signal is ignored on the corresponding chip select.
  • 2 Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped.
  • 3 Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high.
WRITE_MODE1Write Mode
READ_MODE0Read Mode

CS_X1.SMC_SETUPSMC Setup Register

Address
0x4502C010
Reset
0x01010101
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_SETUP29:24NCS Setup Length in READ Access
NRD_SETUP21:16NRD Setup Length
NCS_WR_SETUP13:8NCS Setup Length in WRITE Access
NWE_SETUP5:0NWE Setup Length

CS_X1.SMC_PULSESMC Pulse Register

Address
0x4502C014
Reset
0x01010101
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_PULSE30:24NCS Pulse Length in READ Access
NRD_PULSE22:16NRD Pulse Length
NCS_WR_PULSE14:8NCS Pulse Length in WRITE Access
NWE_PULSE6:0NWE Pulse Length

CS_X1.SMC_CYCLESMC Cycle Register

Address
0x4502C018
Reset
0x00030003
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
NRD_CYCLE24:16Total Read Cycle Length
NWE_CYCLE8:0Total Write Cycle Length

CS_X1.SMC_MODESMC Mode Register

Address
0x4502C01C
Reset
0x10001003
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
PS29:28Page Size
  • 0 4-byte page
  • 1 8-byte page
  • 2 16-byte page
  • 3 32-byte page
PMEN24Page Mode Enabled
TDF_MODE20TDF Optimization
TDF_CYCLES19:16Data Float Time
DBW12Data Bus Width
  • 0 8-bit Data Bus
  • 1 16-bit Data Bus
BAT8Byte Access Type
  • 0 Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1.
  • 1 Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD.
EXNW_MODE5:4NWAIT Mode
  • 0 Disabled-The NWAIT input signal is ignored on the corresponding chip select.
  • 2 Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped.
  • 3 Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high.
WRITE_MODE1Write Mode
READ_MODE0Read Mode

CS_X2.SMC_SETUPSMC Setup Register

Address
0x4502C020
Reset
0x01010101
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_SETUP29:24NCS Setup Length in READ Access
NRD_SETUP21:16NRD Setup Length
NCS_WR_SETUP13:8NCS Setup Length in WRITE Access
NWE_SETUP5:0NWE Setup Length

CS_X2.SMC_PULSESMC Pulse Register

Address
0x4502C024
Reset
0x01010101
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_PULSE30:24NCS Pulse Length in READ Access
NRD_PULSE22:16NRD Pulse Length
NCS_WR_PULSE14:8NCS Pulse Length in WRITE Access
NWE_PULSE6:0NWE Pulse Length

CS_X2.SMC_CYCLESMC Cycle Register

Address
0x4502C028
Reset
0x00030003
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
NRD_CYCLE24:16Total Read Cycle Length
NWE_CYCLE8:0Total Write Cycle Length

CS_X2.SMC_MODESMC Mode Register

Address
0x4502C02C
Reset
0x10001003
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
PS29:28Page Size
  • 0 4-byte page
  • 1 8-byte page
  • 2 16-byte page
  • 3 32-byte page
PMEN24Page Mode Enabled
TDF_MODE20TDF Optimization
TDF_CYCLES19:16Data Float Time
DBW12Data Bus Width
  • 0 8-bit Data Bus
  • 1 16-bit Data Bus
BAT8Byte Access Type
  • 0 Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1.
  • 1 Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD.
EXNW_MODE5:4NWAIT Mode
  • 0 Disabled-The NWAIT input signal is ignored on the corresponding chip select.
  • 2 Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped.
  • 3 Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high.
WRITE_MODE1Write Mode
READ_MODE0Read Mode

CS_X3.SMC_SETUPSMC Setup Register

Address
0x4502C030
Reset
0x01010101
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_SETUP29:24NCS Setup Length in READ Access
NRD_SETUP21:16NRD Setup Length
NCS_WR_SETUP13:8NCS Setup Length in WRITE Access
NWE_SETUP5:0NWE Setup Length

CS_X3.SMC_PULSESMC Pulse Register

Address
0x4502C034
Reset
0x01010101
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
NCS_RD_PULSE30:24NCS Pulse Length in READ Access
NRD_PULSE22:16NRD Pulse Length
NCS_WR_PULSE14:8NCS Pulse Length in WRITE Access
NWE_PULSE6:0NWE Pulse Length

CS_X3.SMC_CYCLESMC Cycle Register

Address
0x4502C038
Reset
0x00030003
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
NRD_CYCLE24:16Total Read Cycle Length
NWE_CYCLE8:0Total Write Cycle Length

CS_X3.SMC_MODESMC Mode Register

Address
0x4502C03C
Reset
0x10001003
Access
read/write
Size
32-bit
9 fields
FieldBitsWhat it does
PS29:28Page Size
  • 0 4-byte page
  • 1 8-byte page
  • 2 16-byte page
  • 3 32-byte page
PMEN24Page Mode Enabled
TDF_MODE20TDF Optimization
TDF_CYCLES19:16Data Float Time
DBW12Data Bus Width
  • 0 8-bit Data Bus
  • 1 16-bit Data Bus
BAT8Byte Access Type
  • 0 Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1.
  • 1 Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD.
EXNW_MODE5:4NWAIT Mode
  • 0 Disabled-The NWAIT input signal is ignored on the corresponding chip select.
  • 2 Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped.
  • 3 Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high.
WRITE_MODE1Write Mode
READ_MODE0Read Mode

SMC_WPMRSMC Write Protection Mode Register

Address
0x4502C0E4
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
WPEN0Write Protect Enable
WPKEY31:8Write Protection Key
  • 5459267 Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

SMC_WPSRSMC Write Protection Status Register

Address
0x4502C0E8
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
WPVSRC23:8Write Protection Violation Source
WPVS0Write Protection Violation Status