PIC32CK2051SG00100 SUPC registers

The 11 registers of SUPC (Supply Controller), from 0x44008000, with their reset value and every field. The PIC32CK2051SG00100 has 6023 registers in 75 peripherals, one page each.

SUPC Supply Controller

INTENCLRInterrupt Enable Clear

Address
0x44008000
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ADDVREGRDY08Additional Regulator ready 0 Interrupt Enable
BORVDDUSB5BORVDDUSB Interrupt Enable
LVDRDY1Low Voltage Detector Ready Interrupt Enable
LVDET0Low Voltage Detector Interrupt Enable

INTENSETInterrupt Enable Set

Address
0x44008004
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ADDVREGRDY08Additional Regulator ready 0 Interrupt Enable
BORVDDUSB5BORVDDUSB Interrupt Enable
LVDRDY1Low Voltage Detector Ready Interrupt Enable
LVDET0Low Voltage Detector Interrupt Enable

INTFLAGInterrupt Flag Status and Clear

Address
0x44008008
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ADDVREGRDY08Additional Regulator ready 0 Interrupt. Set to one if additionnal regulator is ready meaning that output voltage is correct.
BORVDDUSB5BORVDDUSB Interrupt. Set to one if VDDUSB issue is detected.
LVDRDY1Low Voltage Detector Ready Interrupt. Set to one if LVD is ready to operate.
LVDET0Low Voltage Detector Interrupt. Set to one if VDDIO crosses the treshold voltage in the good direction according to LVD.DIR.

STATUSFlag status

Address
0x4400800C
Reset
0x00000000
Access
read only
Size
32-bit
4 fields
FieldBitsWhat it does
ADDVREGRDY08Additional Regulator ready 0 Status. One if voltage is OK. It corresponds to vreg_ready_mv signal of additional regulator.
BORVDDUSB5BORVDDUSB Status. One if VDDUSB is OK. It corresponds to bor_vddusb_n_mv signal of SMOR.
LVDRDY1Low Voltage Detector Ready Status
LVDET0Low Voltage Detector Status.

SYNCBUSYSynchronisation Busy

Address
0x44008010
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
BOR0BOR Synchronization Busy

BORBOR Control

Address
0x44008014
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
BORFILT9:8BOR filtering
  • 0 No digital filtering
  • 1 32us filtering
  • 2 125us filtering
  • 3 250us filtering
DCBORPSEL6:4Duty Cycle BOR Prescaler Select
  • 0 Not Divided
  • 1 Divide clock by 2
  • 2 Divide clock by 4
  • 3 Divide clock by 8
  • 4 Divide clock by 16
  • 5 Divide clock by 32
  • 6 Divide clock by 64
  • 7 Divide clock by 128
ACTION0Action when Threshold Crossed
  • 0 The BOR generates a reset

LVDLVD Control

Address
0x44008018
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
LEVEL19:16Threshold Level. See "pwr_smor_[nn]_v1 DOS" - level section to get details.
RUNSTDBY4Run during Standby
OEVEN3Output Event Enable
DIR2Direction
  • 0 Rising detection
  • 1 Falling detection
ENABLE1Enable

VREGCTRLVREG Control

Address
0x4400801C
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
AVREGSTDBY24Additional Voltage Regulator Configuration
  • 0 Regulator is OFF while in sleep mode equal or deeper than standby mode. It is OFF in hibernate and backup mode as well.
  • 1 Regulator is ON in Standby mode if AVREGEN bit is set. is OFF from Hibernate mode. It is OFF in backup mode as well.
AVREGEN16Additional Voltage Regulator Enable
CPEN9:8Charge Pump Enable and Auto-enable.
LVHIB5Low Voltage Hibernate Enable
  • 0 In Hibernate mode, VDDCORE_BU and VDDCORE_RAM are set to 1.2v.
  • 1 In Hibernate mode, VDDCORE_BU and VDDCORE_RAM are set to 0.8v
LVSTDBY4Low Voltage Standby Enable
  • 0 In standby mode, VDDCORE_BU, VDDCORE_RAM, VDDCORE_SW and optionnaly VDDCOREUSB/PLL are set to 1.2v.
  • 1 In standby mode, VDDCORE_BU, VDDCORE_RAM, VDDCORE_SW and optionnaly VDDCOREUSB/PLL are set to 0.8v.
OFFSTDBY2Off in Standby Control for VREGSW[N-1]. Useful for Riverside only.
  • 0 In standby mode, VREGSW1,2,3 are OFF
  • 1 In standby mode, VREGSW1,2,3 are ON

VREFCTRLVREF Control

Address
0x44008020
Reset
0x00000003
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
TSEN4Temperature Sensor Output Enable
LPHIB1Bandgap and Regulators Low Power Hibernate Enable
  • 0 In hibernate mode, bandgap is set to nominal power mode. As a consequence, enabled regulator(s) are set to nominal power mode.
  • 1 In hibernate mode, bandgap is set to low power mode. As a consequence, enabled regulator(s) are set to low power mode.
LPSTDBY0Bandgap and Regulators Low Power Standby Enable
  • 0 In standby mode, bandgap and enabled regulator(s) are set to nominal power mode.
  • 1 In standby mode, bandgap and enabled regulator(s) are set to low power mode.

BKOUTBackup Output Control

Address
0x44008028
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
TGLOM127:26Toggle Output Mode
  • 0 The output does not toggle.
  • 1 The output toggles on RTC event.
  • 2 The output is set when the device enters backup mode or battery backup mode. The output should then be cleared by software.
TGLOM025:24Toggle Output Mode
  • 0 The output does not toggle.
  • 1 The output toggles on RTC event.
  • 2 The output is set when the device enters backup mode or battery backup mode. The output should then be cleared by software.
SET118Set Output
SET016Set Output
CLR110Clear Output
CLR08Clear Output
EN12Enable Output
EN00Enable Output

BKINBackup Input Control

Address
0x4400802C
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
BKIN1:0Backup Input Value