The 31 registers of SQI (Polaris Serial Quad Interface SIB), from 0x0FFFF000, with their reset value and every field. The PIC32CK2051SG01100 has 6232 registers in 78 peripherals, one page each.
SQI Polaris Serial Quad Interface SIB
CTRLAControl A register
Address
0x0FFFF000
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RUNSTDBY
6
Run in Standby
0 Module is disabled in Standby Sleep mode
1 Module continues to run in Standby Sleep mode
INTENCLRInterrupt Enable Clear Register
Address
0x0FFFF010
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
SQI
0
SQI Interrupt Enable Clear
0 Interrupt Enabled
1 Interrupt Disabled
INTENSETInterrupt Enable Set Register
Address
0x0FFFF014
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
SQI
0
SQI Interrupt Enable Set
0 Interrupt disabled
1 Interrupt enabled
INTFLAGInterrupt Status and Clear Register
Address
0x0FFFF018
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
SQI
0
Read value reflects the state of the interrupt flag. Do not use the interrupt flag and associated mask registers if the EIP already provides similar controls for its interrupts. This feature is design for interrupts created in the SIB or EIP which do not have mask or flag bits. Write to 1 to clear t
SYNCBUSYSyncbusy Register
Address
0x0FFFF020
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
SWRST
0
Software Reset Synchronization Busy
0 SWRST synchronization is not busy
1 SWRST synchronization is busy
XCON1SPI XIP Control1 register
Address
0x0FFFF100
Reset
0x202C0C00
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
SDRCMD
29
SPI TYPE CMD SDR2DDR: This bit is used by the controller only when XIP_SPI_TYPE_CMD_DDR is 1?b1 i.e., when command sent in DDR mode. 0 - The command (XIP_SPI_READ_OPCODE) will take 4 clock cycles. Data will go in both the edges. Used when Flash expecting the cmd in ddr mode. Here the command will g
DDRDATA
28
XIP SPI TYPE DATA DDR 0 - SDR mode, 1 - DDR mode. Based on this field, the boot controller will send the data in SDR/DDR mode.
DDRDUMMY
27
XIP SPI TYPE DUMMY DDR. 0 - SDR mode, 1 - DDR mode. Based on this field, the boot controller will send the dummy bytes in SDR/DDR mode.
DDRMODE
26
XIP SPI TYPE MODE DDR 0 - SDR mode, 1 - DDR mode. Based on this field, the boot controller will send the mode bytes in SDR/DDR mode.
DDRADDR
25
XIP SPI TYPE ADDR DDR 0 - SDR mode, 1 - DDR mode. Based on this field, the boot controller will send the address bytes in SDR/DDR mode.
DDRCMD
24
XIP SPI TYPE CMD DDR 0 - SDR mode, 1 - DDR mode. Based on this field, the boot controller will send the command in SDR/DDR mode.
DUMMYBYTES
23:21
000 - Zero Dummy bytes ,001 - Transmit one dummy byte (8?h ff) ,010 - Transmit two dummy bytes (16?h ffff) ,011 - Transmit three dummy bytes (24?h ffffff) ,111 - Transmit Seven dummy bytes
SPI TYPE DATA: 00 - Single lane mode ,01 - Dual lane mode ,10 - Quad lane mode ,11 - Reserved for Future use Based on this field, the boot controller will receive the data in 1/2/4 lane.
TYPEDUMMY
7:6
SPI TYPE DUMMY: 00 - Single lane mode ,01 - Dual lane mode,10 - Quad lane mode ,11 - Reserved for Future use. Based on this field, the boot controller will send the Dummy in 1/2/4 lane.
TYPEMODE
5:4
SPI TYPE Mode: 00 - Single lane mode, 01 - Dual lane mode, 10 - Quad lane mode, 11 - Reserved for Future use. Based on this field, the boot controller will send the Mode in 1/2/4 lane.
TYPEADDR
3:2
SPI TYPE Address 00 - Single lane mode ,01 - Dual lane mode ,10 - Quad lane mode ,11 - Reserved for Future use Based on this field, the boot controller will send the Address in 1/2/4 lane.
TYPECMD
1:0
SPI TYPE Command - Single lane mode, - Dual lane mode, - Quad lane mode, - Reserved for Future use, Based on this field, the boot controller will send the command in 1/2/4 lane.
XCON2SPI XIP Control2 register
Address
0x0FFFF104
Reset
0x000000A0
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
DEVSEL
12:10
XIP SPI Device Select: This field is used to select a particular SPI device 000 - Select Device0 , 001 - Select Device1 , 010 - Select Device2 , 011 - Select Device3 , 100 - Select Device4 , 101 - Select Device5 , 110 - Select Device6 , 111 - Select Device7
1 - Enabled, 0 - Disabled SPI_ON output pin is controlled by writing to this bit.
DATAEN
21:20
Max Data Lanes 11 - Reserved, 10 - 4, 01 - 2, 00 - 1 SPI_OUT_PIN_EN[3:0] output pins are controlled by writing to these bits.
CONBUFRST
19
Control FIFO Reset A reset pulse is generated when writing 1 to this bit. This bit is Auto clear and SPI Controller will clear this bit. Control fifo pointers will get reset by this reset pulse. Note: Control FIFO reset can be done only after a transaction is complete on spi bus; however if we want
RXBUFRST
18
Receive FIFO Reset A reset pulse is generated when writing 1 to this bit. This bit is Auto clear and SPI Controller will clear this bit. Receive fifo pointers will get reset by this reset pulse. Note: Receive FIFO reset can be done only after a transaction is complete on spi bus; however if we want
TXBUFRST
17
Transmit FIFO Reset A reset pulse is generated when writing 1 to this bit. This bit is Auto clear and SPI Controller will clear this bit. Transmit FIFO pointers will get reset by this reset pulse. Note: Transmit FIFO reset can be done only after a transaction is complete on spi bus; however if we wa
RESET
16
Software Reset Select Bit
AHB_BURST_INCR16_EN
14
This field is used to configure the AHB Master Burst capability. 1 - AHB INCR16 is enabled. 0 - AHB INCR16 is disabled
AHB_BURST_INCR8_EN
13
This field is used to configure the AHB Master Burst capability. 1 - AHB INCR8 is enabled. 0 - AHB INCR8 is disabled
AHB_BURST_INCR4_EN
12
This field is used to configure the AHB Master Burst capability. 1 - AHB INCR4 is enabled. 0 - AHB INCR4 is disabled
BURSTEN
11
This field is used to configure the AHB Master Burst capability. 1 - AHB INCR is enabled 0 - AHB INCR is disabled
HOLD
10
Hold: In Single or Dual lane mode, this bit is used to drive the spiout3 signal. Whenever this bit is high, the controller drives 0 on spiout3 line and sets spimoe3 high (active only during transfer).
WP
9
Write Protect: In single or Dual lane mode, this bit is used to drive the spiout2 signal. Whenever this bit is high, the controller drives 0 on spiout2 line and sets spimoe2 high (active only during transfer).
LSBF
5
Data format on SPI interface 0 = MSBit sent/received first. 1 = LSBit sent/received first. This setting is supeceded by LSBF control bit in Buffer Descriptor during DMA operations.
CPOL
4
Clock polarity 0 = active-high SPICLK (SPICLK low is the idle state) 1 = active-low SPICLK (SPICLK high is the idle state)
CPHA
3
Clock phase (selects the transfer format) 0 = SPICLK starts toggling at the middle of 1st data bit. 1 = SPICLK starts toggling at the start of 1st data bit.
MODE
2:0
Mode Select The default value of this field is 0. After power on reset, the controller enters boot mode. 000 - Boot mode. The CSR registers are loaded with boot strap values. 001 - PIO mode. The controller is controlled by the CPU in PIO mode. 010 - DMA mode. 011 - XIP mode. When this mode is enter
CSEN
31:24
1 - Chip Select is used 0 - Chip Select is not used SPI_CS[7] for CS7, SPI_CS[6] for CS6, SPI_CS[5] for CS5, SPI_CS[4] for CS4, SPI_CS[3] for CS3, SPI_CS[2] for CS2, SPI_CS[1] for CS1, SPI_CS[0] for CS0. SPI_CS_PIN_EN[7:0/3:0] output pins are controlled by writing to these bits.
CONSPI Control register
Address
0x0FFFF10C
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
SCHECK
24
Status Check This bit is mainly used for Programming or Erase operations. 0 - do not check status, 1 - check status. If this bit is set to 1, the hardware will issue the status command automatically after the current operation and wait for busy bit to clear. The hardware will issue the next command
DDRMODE
23
SDR_DDR: 0 - SDR mode, 1 - DDR mode. Note: For Michigan Ax versions this bit is Reserved and should be kept 0.
DASSERT
22
Chip Select Assert 0 - CS is not de-asserted after transmission/reception of specified number of bytes in the control register 1 - CS is de-asserted after transmission/reception of specified number of bytes in the control register
DEVSEL
21:20
SPI Device Select: This field along with bit25 is used to select a particular SPI device. Note: For Michigan Ax versions, extension by bit25 is NOT used (only 4 devices are selectable, by bits 21:20 here).
LANEMODE
19:18
SPI Lane mode 00 - Single lane mode ,01 - Dual lane mode ,10 - Quad lane mode ,11 - Reserved for Future use
CMDINIT
17:16
This signal indicates the command initiation mode. If it is Transmit, Commands are initiated based on writes to transmit register or the contents of TX FIFO. If the CMD_INIT is Receive, commands are initiated based on reads to Read register or RX FIFO availability. 00 = Reserved. 01 = Initiate Tran
TXRXCOUNT
15:0
This bit specifies the total number of bytes to transmit or receive (based on CMD_INIT field). ,16?d 0 - Reserved,16?d 1 - 1byte to transmit/receive ,16?d 2 - 2bytes to transmit/receive NOTE: Count must be programmed to non-zero value prior to initiating transaction
CLKCONSPI Clock Control register
Address
0x0FFFF110
Reset
0x00000001
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
CLKDIV
18:8
SPI Clock Frequency Select 400h - base clock divided by 2048 ,200h - base clock divided by 1024 ,100h - base clock divided by 512 ,080h - base clock divided by 256 ,040h - base clock divided by 128 ,020h - base clock divided by 64 ,010h - base clock divided by 32 ,008h - base clock divided by 16 ,0
STABLE
1
After Reset, this bit is set to 1 when SPI Clock is stable after writing Internal Clock Enable in this register to 1. The Clock Stable indication will continue unless the Clock Divisor Value is changed, in which case it will wait until Clock is stable again. Stability is rea
EN
0
This bit is set to 0 when the SPI Driver is not using the SPI Controller. The SPI Controller should stop its internal clock to go very low power state. Still, registers will be able to be read and written. Clock starts to oscillate when this bit is set to 1. When clock oscillation is stable, the S
CMDTHRSPI command threshold register
Address
0x0FFFF114
Reset
0x00000101
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
TXCMDTHR
15:8
In TX Initiation Mode, SPI Performs a transmit Operation when TX_CMD_THRES bytes are present in the TX FIFO. This should usually be set to 1 for normal flash commands, and is desired to be set to a higher value for page programming. NOTE: Value of 8?d0 should be treated as Reserved (illegal) for thi
RXCMDTHR
7:0
In RX initiation mode, SPI attempts to perform receive fetch operations until RX_CMD_THRES bytes of space remain in the receive buffer. If space for RX_CMD_THRES bytes is not present in the FIFO, then SPI would not initiate any transfer. RX_CMD_THRES should only be programmed when RX is not active,
INTTHRSPI Interrupt Threshold register
Address
0x0FFFF118
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
TXINTTHR
15:8
Transmit Interrupt is set when Transmit FIFO has equal or more space than TX_INT_THRES bytes.
RXINTTHR
7:0
Receive Interrupt is set when Receive FIFO CNT is larger than or equal to RX_INT_THRES Value.
INTENSPI Interrupt Enable Register
Address
0x0FFFF11C
Reset
0x000000AD
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
DMAEIE
11
Master Error Interrupt Enable
PKTCOMPIE
10
Packet completion Interrupt
BDDONEIE
9
Current Buffer Descriptor Interrupt Enable
CONTHRIE
8
Control Buffer Threshold Interrupt Enable
CONEMPTYIE
7
Control Buffer Empty Interrupt Enable
CONFULLIE
6
Control Buffer Full Interrupt Enable
RXTHRIE
5
Enable Interrupt to be generated when the RX FIFO has data more than or equal to RX_INT_THRES words. In case of Boot/XIP mode, the power on reset value of RX buffer threshold is zero. So this bit will be set to 1, immediately after power on reset, till a read request on the AHB Bus.
RXFULLIE
4
RX FIFO Full Interrupt Enable.
RXEMPTYIE
3
RX FIFO Empty Interrupt Enable.
TXTHRIE
2
Enable Interrupt to be generated when the TX FIFO has space equal to or more than TX_INT_THRES words.
TXFULLIE
1
TX FIFO Full Interrupt Enable.
TXEMPTYIE
0
TX FIFO Empty Interrupt Enable.
INTSTATSPI Interrupt Status Register
Address
0x0FFFF120
Reset
0x000000AD
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
DMAEIF
11
Master Error Interrupt
PKTCOMPIF
10
Packet completion Interrupt
BDDONEIF
9
BDP sets this bit to '1' after current buffer descriptor is processed
CONTHRIF
8
Control Buffer Threshold Interrupt
CONEMPTYIF
7
Control Buffer Empty Interrupt
CONFULLIF
6
Control Buffer Full Interrupt
RXTHRIF
5
Interrupt to be generated when the RX FIFO has data more than or equal to RX_INT_THRES words. In case of Boot/XIP mode, the power on reset value of RX buffer threshold is zero. So this bit will be set to 1, immediately after power on reset, till a read request on the AHB Bus.
RXFULLIF
4
RX FIFO Full Interrupt.
RXEMPTYIF
3
RX FIFO Empty Interrupt.
TXTHRIF
2
Interrupt to be generated when the TX FIFO has space equal to or more than TX_INT_THRES words.
TXFULLIF
1
TX FIFO Full Interrupt.
TXEMPTYIF
0
TX FIFO Empty Interrupt.
TXDATASPI Transmit Data Register
Address
0x0FFFF124
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXDATA
31:0
Data is loaded into this register before being transmitted. Just prior to the beginning of a data transfer, the data in TX_DATA is loaded into the shift register. This register is used as a window to write data into Transmit buffer.
RXDATASPI Receive Data Register
Address
0x0FFFF128
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
RXDATA
31:0
At the end of a data transfer, the data in the shift register is loaded into RX_DATA register. This register is used as a window to read data from Receive buffer.
STAT1SPI Status1 Register
Address
0x0FFFF12C
Reset
0x01000000
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
RXBUFCNT
15:0
Number of Words of Read Data in the FIFO.
TXBUFFREE
31:16
Number of Words of Space available in the TX FIFO. Max value equals value of MEM_SIZE_BYTES parameter. Default value is Max
STAT2SPI status 2 register
Address
0x0FFFF130
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
Field
Bits
What it does
CMDSTAT
17:16
Reflect the (internal state machine) CMD_INIT value. Indicates whether the controller is in Transmit/Receive/IDLE state. 2?b00 - IDLE ,2?b01 - Transmit ,2?b10 - Receive ,2?b11 - Reserved
CONAVAIL
9:7
Indicates the number of entries in Control Buffer remaining. NOTE: This field not present in Michigan Ax versions. Treat as Reserved.
SQID3
6
SPI Data bus: This status is used to check the SPI DATA line level for Debugging. Bit3 - SPI_IO0 ,Bit4 - SPI_IO1 ,Bit5 - SPI_IO2 ,Bit6 - SPI_IO3
SQID2
5
SPI Data bus: This status is used to check the SPI DATA line level for Debugging. Bit3 - SPI_IO0 ,Bit4 - SPI_IO1 ,Bit5 - SPI_IO2 ,Bit6 - SPI_IO3
SQID1
4
SPI Data bus: This status is used to check the SPI DATA line level for Debugging. Bit3 - SPI_IO0 ,Bit4 - SPI_IO1 ,Bit5 - SPI_IO2 ,Bit6 - SPI_IO3
SQID0
3
SPI Data bus: This status is used to check the SPI DATA line level for Debugging. Bit3 - SPI_IO0 ,Bit4 - SPI_IO1 ,Bit5 - SPI_IO2 ,Bit6 - SPI_IO3
RXUN
1
This bit would get set when RX FIFO UNDERFLOW happens. S/W needs to monitor RX_FIFO_CNT when emptying RX_FIFO to make sure RX FIFO doesn?t under flow or in case UNDERFLOW bit gets set, then RX_FIFO_RST (bit 18 of SPI Configuration register) must be set which would then clear RX FIFO pointers and he
TXOV
0
This bit would get set when TX FIFO OVERFLOW happens. S/W needs to monitor TX_FIFO_FREE when filling TX_FIFO to make sure TX FIFO doesn?t over flow or in case OVERFLOW bit gets set, then TX_FIFO_RST (bit 17 of SPI Configuration register) should be set which would then clear TX FIFO pointers and henc
BDCONBD_CTRL Register
Address
0x0FFFF134
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
START
2
Setting this bit to '1' would start BDP (Buffer Descriptor Processor) to fetch a descriptor and hence this bit should be enabled only after all the DMA descriptor programming is done. Hardware clears this bit automatically after one clock cycle.
POLLEN
1
Setting this bit would cause Buffer Descriptor processor (BDP) to poll for descriptor valid till descriptor valid bit is set or till poll counter expires based on value programmed in BD_POLL_CTRL register.
DMAEN
0
DMA Enable Bit 1 - Enabled, 0 - Disabled
BDCURADDBD_CURR_ADDR Register
Address
0x0FFFF138
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
BDCURRADDR
31:0
This register field contains the current descriptor address being processed by Buffer Descriptor Processor (BDP)
BDBASEADDBD_BASE_ADDR register
Address
0x0FFFF140
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
BDADDR
31:0
This register field contains the base address of the DMA. This register must be updated only when the DMA is IDLE.
BDSTATBD_STATUS Register
Address
0x0FFFF144
Reset
0x00000000
Access
read only
Size
32-bit
4 fields
Field
Bits
What it does
BDSTATE
21:18
This register field contains current BDP state : 0 IDLE, 1 Descriptor fetch Request Pending, 2 BD loading, 3 Data phase , 4 Descriptor Done, 5 Fetched BD is disabled, 6 Wait for Control Buffer Available, 7 Wait for AHB Error Acknowledgement
DMASTART
17
This register field would indicate whether DMA has started or not, if bit it set '1', then it indicates DMA start has happened. Value of '0' would indicate that DMA hasn't started.
DMAACTV
16
A value of '1' would indicate that Buffer Descriptor Processor (BDP) is not Idle. Value of '0' would indicate that BDP is in IDLE state
BDCON
15:0
This register field contains the current Descriptor control information. Bits [31:16] of BD_CTRL field of current descriptor are indicated in this register field.
BDPOLLCONBD_POLL_CTRL Register
Address
0x0FFFF148
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
POLLCON
15:0
Number of cycles that BDP block would wait before re-fetching the Descriptor control word if the previous descriptor fetched was disabled
BDTXDSTATBD_TX_DMA_STATUS Register
Address
0x0FFFF14C
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
TXBUFCNT
23:16
This register field gives the information about the internal transmit FIFO space.
TXCURBUFLEN
15:0
This register field gives the length of the current buffer transmit length
BDRXDSTATBD_RX_DMA_STATUS Register
Address
0x0FFFF150
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
RXBUFCNT
16
This register field gives the information about the internal receive FIFO space.
RXCURBUFLEN
15:0
This register field gives the length of the current buffer receive length
THRSPI Control threshold register
Address
0x0FFFF154
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
THRES
2:0
SPI Control Threshold Value. SPI Control Threshold Interrupt is asserted, whenever larger than SPI Control Threshold amount of space available in SPI Control Buffer.
INTSIGENSPI Interrupt Signal Enable Register
Address
0x0FFFF158
Reset
0x000008AD
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
DMAEISE
11
Master Error Interrupt Signal Enable
PKTCOMPISE
10
Packet completion Interrupt Signal Enable
BDDONEISE
9
Current Buffer Descriptor Interrupt Signal Enable
CONTHRISE
8
Control Buffer Threshold Interrupt Signal Enable
CONEMPTYISE
7
Control Buffer Empty Interrupt Signal Enable
CONFULLISE
6
Control Buffer Full Interrupt Signal Enable
RXTHRISE
5
Signal Enable Interrupt to be generated when the RX FIFO has data more than or equal to RX_INT_THRES words. In case of Boot/XIP mode, the power on reset value of RX buffer threshold is zero. So this bit will be set to 1, immediately after power on reset, till a read request on the AHB Bus.
RXFULLISE
4
RX FIFO Full Interrupt Signal Enable.
RXEMPTYISE
3
RX FIFO Empty Interrupt Signal Enable.
TXTHRISE
2
Signal Enable Interrupt to be generated when the TX FIFO has space equal to or more than TX_INT_THRES words.
TXFULLISE
1
TX FIFO Full Interrupt Signal Enable.
TXEMPTYISE
0
TX FIFO Empty Interrupt Signal Enable.
TAPCONTap Control Register
Address
0x0FFFF15C
Reset
0x00110021
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
DDRCLKINDLY
29:24
Used only in DDR mode. This field is used to add tap delay cells on the spi clock input. Based on the mode of operation (SDR Vs DDR), the controller dynamically picks the appropriate delay values (CLK_IN_DLY_CNT Vs CLK_IN_ALT_DLY_CNT).
SDRDATINDLY
23:20
Used only in SDR mode. This field is used to add tap delay cells on the Data input. Based on the mode of operation (SDR Vs DDR), the controller dynamically picks the appropriate delay values (DATA_IN_ALT_DLY_CNT Vs DATA_IN_DLY_CNT).
DDRDATINDLY
19:16
Used only in DDR mode. This field is used to add tap delay cells on the data input. Based on the mode of operation (SDR Vs DDR), the controller dynamically picks the appropriate delay values (DATA_IN_ALT_DLY_CNT Vs DATA_IN_DLY_CNT).
SDRCLKINDLY
13:8
Used only in SDR mode. This field is used to add tap delay cells on the spi clock input. Based on the mode of operation (SDR Vs DDR), the controller dynamically picks the appropriate delay values (CLK_IN_DLY_CNT Vs CLK_IN_ALT_DLY_CNT).
DATAOUTDLY
7:4
Used to add delay on spi data outputs (1/2/4lanes). 16 taps available.
CLKOUTDLY
3:0
Used to add delay on spi clock output.16 taps available.
MEMSTATSPI Status Control Register
Address
0x0FFFF160
Reset
0x00010005
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
STATPOS
20
Indicates whether the BUSY bit position in Status Register of flash is 0 or 7. 1?b0 - 0th bit position (bit 0 is valid for busy status), 1?b1 - 7th bit position (bit7 is valid for busy status) The Controller continuously reads the Status register value from flash until this bit which indicates the f
TYPESTAT
19:18
Status Lane: Indicates the number of lanes (single/dual/quad) in which the Status command/ Read Status Register value is transmitted to /received from flash. 2?b00 - single lane, 2?b01 - dual lane, 2?b10 - quad lane
STATBYTES
17:16
No. of bytes to send: 00 - Reserved ,01 - 1 byte ,10 - 2 bytes ,11 - Reserved
STATCMD
15:0
Status Data: The first byte to be sent must be in LSB. For example if the user wants to send 0F first and 0C second, then we should program 16?h0C0F.
XCON3SPI XIP Control 3 Register
Address
0x0FFFF164
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
INIT1SCHECK
28
SPI Init1 Status Check: 0 - do not check status, 1 - check status. If this bit is set to 1, the hardware will issue the status command automatically after the current operation and wait for busy bit to clear. The hardware will issue the next command only after this Status check phase. Note: The Stat
INIT1COUNT
27:26
2bit SPI INIT1 Count. Indicates whether 1, 2 or 3 bytes of INIT1 Code value are being sent.
INIT1TYPE
25:24
SPI TYPE INIT1: 00 - Single lane mode , 01 - Dual lane mode , 10 - Quad lane mode , 11 - Reserved for Future use. Based on this field, the boot controller will send the INIT1 Code in 1/2/4 lane.
INIT1CMD3
23:16
8bit SPI Init1 Code3 value.
INIT1CMD2
15:8
8bit SPI Init1 Code2 value.
INIT1CMD1
7:0
8bit SPI Init1 Code1 value.
XCON4SPI XIP Control4 Register
Address
0x0FFFF168
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
INIT2SCHECK
28
SPI Init2 Status Check: 0 - do not check status 1 - check status If this bit is set to 1, the hardware will issue the status command automatically after thecurrent operation and wait for busy bit to clear. The hardware will issue the next command only after this Status check phase. Note: The Status
INIT2COUNT
27:26
2bit SPI INIT2 Count. Indicates whether 1, 2 or 3 bytes of INIT2 Code value are being sent.
INIT2TYPE
25:24
SPI TYPE INIT2: 00 - Single lane mode. 01 - Dual lane mode. 10 - Quad lane mode. 11 - Reserved for Future use. Based on this field, the boot controller will send the INIT2 Code in 1/2/4 lane.
BETA