PIC32CM1216LE00048 PM registers

The 7 registers of PM (Power Manager), from 0x40000401, with their reset value and every field. The PIC32CM1216LE00048 has 1312 registers in 40 peripherals, one page each.

PM Power Manager

SLEEPCFGSleep Configuration

Address
0x40000401
Reset
0x02
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2SLEEPMODE2
  7. 1SLEEPMODE1
  8. 0SLEEPMODE0
1 field
FieldBitsWhat it does
SLEEPMODE2:0Sleep Mode
  • 2 CPU, AHBx, and APBx clocks are OFF
  • 4 ALL clocks are OFF, unless requested by sleepwalking peripheral
  • 6 All power domains are powered OFF

PLCFGPerformance Level Configuration

Address
0x40000402
Reset
0x00
Access
read/write
  1. 7PLDIS
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1PLSEL1
  8. 0PLSEL0
2 fields
FieldBitsWhat it does
PLDIS7Performance Level Disable
PLSEL1:0Performance Level Select
  • 0 Performance Level 0
  • 2 Performance Level 2

PWCFGPower Configuration

Address
0x40000403
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1RAMPSWC1
  8. 0RAMPSWC0
1 field
FieldBitsWhat it does
RAMPSWC1:0RAM Power Switch Configuration
  • 0 SRAM Retention: 64KB (512KB Flash), 32KB (256KB Flash), 16KB (128KB Flash)
  • 1 SRAM Retention: 48KB (512KB Flash), 32KB (256KB Flash), 12KB (128KB Flash)
  • 2 SRAM Retention: 32KB (512KB Flash), 32KB (256KB Flash), 8KB (128KB Flash)
  • 3 SRAM Retention: 16KB (512KB Flash), 16KB (256KB Flash), 4KB (128KB Flash)

INTENCLRInterrupt Enable Clear

Address
0x40000404
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0PLRDY
1 field
FieldBitsWhat it does
PLRDY0Performance Level Interrupt Enable

INTENSETInterrupt Enable Set

Address
0x40000405
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0PLRDY
1 field
FieldBitsWhat it does
PLRDY0Performance Level Ready interrupt Enable

INTFLAGInterrupt Flag Status and Clear

Address
0x40000406
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2–
  7. 1–
  8. 0PLRDY
1 field
FieldBitsWhat it does
PLRDY0Performance Level Ready

STDBYCFGStandby Configuration

Address
0x40000408
Reset
0x0000
Access
read/write
Size
16-bit
5 fields
FieldBitsWhat it does
BBIASTR12Back Bias for Trust RAM
BBIASHS10Back Bias for SRAM
VREGSMOD7:6Voltage Regulator Standby mode
  • 0 Automatic mode
  • 1 Performance oriented
  • 2 Low Power oriented
DPGPDSW4Dynamic Power Gating for PDSW
  • 0 Dynamic Power Gating disabled
  • 1 Dynamic Power Gating enabled
PDCFG0Power Domain Configuration
  • 0 PDSW power domain switching is handled by hardware.
  • 1 PDSW is forced ACTIVE.