The 11 registers of NVMCTRL (Non-Volatile Memory Controller), from 0x41004000, with their reset value and every field. The PIC32CM1216MC00048 has 1146 registers in 44 peripherals, one page each.
NVMCTRL Non-Volatile Memory Controller
CTRLAControl A
Address
0x41004000
Reset
0x0000
Access
read/write
Size
16-bit
2 fields
Field
Bits
What it does
CMDEX
15:8
Command Execution
165 Execution Key
CMD
6:0
Command
2 Erase Row - Erases the row addressed by the ADDR register.
4 Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.
5 Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.
6 Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.
26 Data Flash Erase Row - Erases the row addressed by the ADDR register.
28 Data Flash Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.
64 Lock Region - Locks the region containing the address location in the ADDR register.
65 Unlock Region - Unlocks the region containing the address location in the ADDR register.
66 Sets the power reduction mode.
67 Clears the power reduction mode.
68 Page Buffer Clear - Clears the page buffer.
69 Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row.
70 Invalidate all cache lines.
127 Set Chip Erase Hard Lock (SCEHL) flash controller command
CTRLBControl B
Address
0x41004004
Reset
0x00000080
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
CACHEDIS
19:18
Cache Disable
0 The Data Flash cache is disabled, the main array cache is enabled
1 The Data Flash cache is disabled, the main array cache is disabled
2 The Data Flash cache is enabled, the main array cache is enabled
3 The Data Flash cache is enabled, the main array cache is disabled
READMODE
17:16
NVM Read Mode
0 The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.
1 Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.
2 The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings.
SLEEPPRM
9:8
Power Reduction Mode during Sleep
0 NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access.
1 NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep.
3 Auto power reduction disabled.
MANW
7
Manual Write
RWS
4:1
NVM Read Wait States
0 Single Auto Wait State
1 Half Auto Wait State
2 Dual Auto Wait State
PARAMNVM Parameter
Address
0x41004008
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
PSZ
18:16
Page Size
0 8 bytes
1 16 bytes
2 32 bytes
3 64 bytes
4 128 bytes
5 256 bytes
6 512 bytes
7 1024 bytes
NVMP
15:0
NVM Pages
DFP
31:20
Data Flash Pages
INTENCLRInterrupt Enable Clear
Address
0x4100400C
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
ERROR
1
Error Interrupt Enable
READY
0
NVM Ready Interrupt Enable
INTENSETInterrupt Enable Set
Address
0x41004010
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
ERROR
1
Error Interrupt Enable
READY
0
NVM Ready Interrupt Enable
INTFLAGInterrupt Flag Status and Clear
Address
0x41004014
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
ERROR
1
Error
0 No errors have been received since the last clear
1 At least one error has occurred since the last clear
READY
0
NVM Ready
0 The NVM controller is busy programming or erasing.
1 The NVM controller is ready to accept a new command
BETA