The 23 registers of DMAC (Direct Memory Access Controller), from 0x41006000, with their reset value and every field. The PIC32CM1216PL10032 has 642 registers in 32 peripherals, one page each.
DMAC Direct Memory Access Controller
CTRLControl
Address
0x41006000
Reset
0x0000
Access
read/write
Size
16-bit
7 fields
Field
Bits
What it does
LVLEN3
11
Priority Level 3 Enable
LVLEN2
10
Priority Level 2 Enable
LVLEN1
9
Priority Level 1 Enable
LVLEN0
8
Priority Level 0 Enable
CRCENABLE
2
CRC Enable
DMAENABLE
1
DMA Enable
SWRST
0
Software Reset
CRCCTRLCRC Control
Address
0x41006002
Reset
0x0000
Access
read/write
Size
16-bit
3 fields
Field
Bits
What it does
CRCSRC
13:8
CRC Input Source
0 No action
1 I/O interface
32 DMA Channel 0
33 DMA Channel 1
CRCPOLY
3:2
CRC Polynomial Type
0 CRC-16 (CRC-CCITT)
1 CRC32 (IEEE 802.3)
CRCBEATSIZE
1:0
CRC Beat Size
0 8-bit bus transfer
1 16-bit bus transfer
2 32-bit bus transfer
CRCDATAINCRC Data Input
Address
0x41006004
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CRCDATAIN
31:0
CRC Data Input
CRCCHKSUMCRC Checksum
Address
0x41006008
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CRCCHKSUM
31:0
CRC Checksum
CRCSTATUSCRC Status
Address
0x4100600C
Reset
0x00
Access
read/write
7–
6–
5–
4–
3–
2–
1CRCZERO
0CRCBUSY
2 fields
Field
Bits
What it does
CRCZERO
1
CRC Zero
CRCBUSY
0
CRC Module Busy
DBGCTRLDebug Control
Address
0x4100600D
Reset
0x00
Access
read/write
7–
6–
5–
4–
3–
2–
1–
0DBGRUN
1 field
Field
Bits
What it does
DBGRUN
0
Debug Run
QOSCTRLQuality of Service Control
Address
0x4100600E
Reset
0x2A
Access
read/write
7–
6–
5DQOS1
4DQOS0
3FQOS1
2FQOS0
1WRBQOS1
0WRBQOS0
3 fields
Field
Bits
What it does
DQOS
5:4
Data Transfer Quality of Service
0 Background (no sensitive operation)
1 Sensitive Bandwidth
2 Sensitive Latency
3 Critical Latency
FQOS
3:2
Fetch Quality of Service
0 Background (no sensitive operation)
1 Sensitive Bandwidth
2 Sensitive Latency
3 Critical Latency
WRBQOS
1:0
Write-Back Quality of Service
0 Background (no sensitive operation)
1 Sensitive Bandwidth
2 Sensitive Latency
3 Critical Latency
SWTRIGCTRLSoftware Trigger Control
Address
0x41006010
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
SWTRIG1
1
Channel 1 Software Trigger
SWTRIG0
0
Channel 0 Software Trigger
PRICTRL0Priority Control 0
Address
0x41006014
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
LVLPRI3
28:24
Level 3 Channel Priority Number
0 DMA Channel 0
1 DMA Channel 1
RRLVLEN2
23
Level 2 Round-Robin Arbitration Enable
LVLPRI2
20:16
Level 2 Channel Priority Number
0 DMA Channel 0
1 DMA Channel 1
RRLVLEN1
15
Level 1 Round-Robin Arbitration Enable
LVLPRI1
12:8
Level 1 Channel Priority Number
0 DMA Channel 0
1 DMA Channel 1
RRLVLEN0
7
Level 0 Round-Robin Arbitration Enable
LVLPRI0
4:0
Level 0 Channel Priority Number
0 DMA Channel 0
1 DMA Channel 1
RRLVLEN3
31
Level 3 Round-Robin Arbitration Enable
INTPENDInterrupt Pending
Address
0x41006020
Reset
0x0000
Access
read/write
Size
16-bit
7 fields
Field
Bits
What it does
PEND
15
Pending
BUSY
14
Busy
FERR
13
Fetch Error
SUSP
10
Channel Suspend
TCMPL
9
Transfer Complete
TERR
8
Transfer Error
ID
4:0
Channel ID
0 DMA Channel 0
1 DMA Channel 1
INTSTATUSInterrupt Status
Address
0x41006024
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
CHINT1
1
Channel 1 Pending Interrupt
CHINT0
0
Channel 0 Pending Interrupt
BUSYCHBusy Channels
Address
0x41006028
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
BUSYCH1
1
Busy Channel 1
BUSYCH0
0
Busy Channel 0
PENDCHPending Channels
Address
0x4100602C
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
PENDCH1
1
Pending Channel 1
PENDCH0
0
Pending Channel 0
ACTIVEActive Channel and Levels
Address
0x41006030
Reset
0x00000000
Access
read only
Size
32-bit
7 fields
Field
Bits
What it does
ABUSY
15
Active Channel Busy
ID
12:8
Active Channel ID
0 DMA Channel 0
1 DMA Channel 1
LVLEX3
3
Level 3 Channel Trigger Request Executing
LVLEX2
2
Level 2 Channel Trigger Request Executing
LVLEX1
1
Level 1 Channel Trigger Request Executing
LVLEX0
0
Level 0 Channel Trigger Request Executing
BTCNT
31:16
Active Channel Block Transfer Count
BASEADDRDescriptor Memory Section Base Address
Address
0x41006034
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
BASEADDR
31:0
Descriptor Memory Base Address
WRBADDRWrite-Back Memory Section Base Address
Address
0x41006038
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
WRBADDR
31:0
Write-Back Memory Base Address
CHIDChannel ID
Address
0x4100603F
Reset
0x00
Access
read/write
7–
6–
5–
4ID4
3ID3
2ID2
1ID1
0ID0
1 field
Field
Bits
What it does
ID
4:0
Channel ID
0 DMA Channel 0
1 DMA Channel 1
CHCTRLAChannel Control A
Address
0x41006040
Reset
0x00
Access
read/write
7–
6RUNSTDBY
5–
4–
3–
2–
1ENABLE
0SWRST
3 fields
Field
Bits
What it does
RUNSTDBY
6
Channel run in standby
ENABLE
1
Channel Enable
SWRST
0
Channel Software Reset
CHCTRLBChannel Control B
Address
0x41006044
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
CMD
25:24
Software Command
0 No action
1 Channel suspend operation
2 Channel resume operation
TRIGACT
23:22
Trigger Action
0 One trigger required for each block transfer
2 One trigger required for each beat transfer
3 One trigger required for each transaction
TRIGSRC
15:8
Trigger Source
0 Only software/event triggers
1 SERCOM0 RX Trigger
2 SERCOM0 TX Trigger
3 SERCOM1 RX Trigger
4 SERCOM1 TX Trigger
5 TC0 Overflow Trigger
6 TC0 Match/Compare 0 Trigger
7 TC0 Match/Compare 1 Trigger
8 TC1 Overflow Trigger
9 TC1 Match/Compare 0 Trigger
10 TC1 Match/Compare 1 Trigger
11 TC2 Overflow Trigger
12 TC2 Match/Compare 0 Trigger
13 TC2 Match/Compare 1 Trigger
14 TCC0 Overflow Trigger
15 TCC0 Match/Compare 0 Trigger
16 TCC0 Match/Compare 1 Trigger
17 TCC0 Match/Compare 2 Trigger
18 TCC0 Match/Compare 3 Trigger
19 ADC0 Restult Ready Trigger
20 ADC0 Sample Ready Trigger
21 DSU Debug Communication Channel 0
22 DSU Debug Communication Channel 1
LVL
7:5
Channel Arbitration Level
0 Channel priority level 0
1 Channel priority level 1
2 Channel priority level 2
3 Channel priority level 3
EVOE
4
Channel Event Output Enable
EVIE
3
Channel Event Input Enable
EVACT
2:0
Event Input Action
0 No action
1 Normal transfer and conditional transfer on strobe trigger
BETA