The 18 registers of GCLK (Generic Clock Controller), from 0x40001C04, with their reset value and every field. The PIC32CM1216PL10032 has 642 registers in 32 peripherals, one page each.
GCLK Generic Clock Controller
SYNCBUSYSynchronization Busy
Address
0x40001C04
Reset
0x00000000
Access
read only
Size
32-bit
4 fields
Field
Bits
What it does
GENCTRL3
5
Generator Control 3 Synchronization Busy
GENCTRL2
4
Generator Control 2 Synchronization Busy
GENCTRL1
3
Generator Control 1 Synchronization Busy
GENCTRL0
2
Generator Control 0 Synchronization Busy
GENCTRL0Generator Control
Address
0x40001C20
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
RUNSTDBY
13
Run in Standby
DIVSEL
12
Divide Selection
0 The Generator clock frequency equals the clock source frequency divided by GENCTRL[n].DIV
1 The Generator clock frequency equals the clock source frequency divided by 2(GENCTRL[n].DIV + 1)
OE
11
Output Enable
OOV
10
Output Off Value
IDC
9
Improve Duty Cycle
GENEN
8
Generator Enable
SRC
4:0
Generator Clock Source Selection
0 OSCHF oscillator output
1 Generator input pad
2 Generic clock generator 1 output
3 OSC32K oscillator output
4 XOSC32K oscillator output
DIV
31:16
Division Factor
GENCTRL1Generator Control
Address
0x40001C24
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
RUNSTDBY
13
Run in Standby
DIVSEL
12
Divide Selection
0 The Generator clock frequency equals the clock source frequency divided by GENCTRL[n].DIV
1 The Generator clock frequency equals the clock source frequency divided by 2(GENCTRL[n].DIV + 1)
OE
11
Output Enable
OOV
10
Output Off Value
IDC
9
Improve Duty Cycle
GENEN
8
Generator Enable
SRC
4:0
Generator Clock Source Selection
0 OSCHF oscillator output
1 Generator input pad
2 Generic clock generator 1 output
3 OSC32K oscillator output
4 XOSC32K oscillator output
DIV
31:16
Division Factor
GENCTRL2Generator Control
Address
0x40001C28
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
RUNSTDBY
13
Run in Standby
DIVSEL
12
Divide Selection
0 The Generator clock frequency equals the clock source frequency divided by GENCTRL[n].DIV
1 The Generator clock frequency equals the clock source frequency divided by 2(GENCTRL[n].DIV + 1)
OE
11
Output Enable
OOV
10
Output Off Value
IDC
9
Improve Duty Cycle
GENEN
8
Generator Enable
SRC
4:0
Generator Clock Source Selection
0 OSCHF oscillator output
1 Generator input pad
2 Generic clock generator 1 output
3 OSC32K oscillator output
4 XOSC32K oscillator output
DIV
31:16
Division Factor
GENCTRL3Generator Control
Address
0x40001C2C
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
RUNSTDBY
13
Run in Standby
DIVSEL
12
Divide Selection
0 The Generator clock frequency equals the clock source frequency divided by GENCTRL[n].DIV
1 The Generator clock frequency equals the clock source frequency divided by 2(GENCTRL[n].DIV + 1)