PIC32CM1216PL10048 TCC0 registers

The 28 registers of TCC0 (Timer/Counter for Control Applications), from 0x42001800, with their reset value and every field. The PIC32CM1216PL10048 has 702 registers in 32 peripherals, one page each.

TCC0 Timer/Counter for Control Applications

CTRLAControl A

Address
0x42001800
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
CPTEN327Capture Channel 3 Enable
CPTEN226Capture Channel 2 Enable
CPTEN125Capture Channel 1 Enable
CPTEN024Capture Channel 0 Enable
DMAOS23DMA One-Shot Trigger Mode
FCYCLE16Full Cycle Enable
ALOCK14Auto Lock
PRESCSYNC13:12Prescaler and Counter Synchronization
  • 0 Reload or reset Counter on the next GCLK
  • 1 Reload or reset Counter on the next prescaler clock
  • 2 Reload or reset Counter on the next GCLK and reset prescaler counter
RUNSTDBY11Run in Standby
PRESCALER10:8Prescaler
  • 0 Prescaler: GCLK_TCC
  • 1 Prescaler: GCLK_TCC/2
  • 2 Prescaler: GCLK_TCC/4
  • 3 Prescaler: GCLK_TCC/8
  • 4 Prescaler: GCLK_TCC/16
  • 5 Prescaler: GCLK_TCC/64
  • 6 Prescaler: GCLK_TCC/256
  • 7 Prescaler: GCLK_TCC/1024
ENABLE1Enable
SWRST0Software Reset

CTRLBCLRControl B Clear

Address
0x42001804
Reset
0x00
Access
read/write
  1. 7CMD2
  2. 6CMD1
  3. 5CMD0
  4. 4IDXCMD1
  5. 3IDXCMD0
  6. 2ONESHOT
  7. 1LUPD
  8. 0DIR
5 fields
FieldBitsWhat it does
CMD7:5TCC Command
IDXCMD4:3Ramp Index Command
ONESHOT2One-Shot
LUPD1Lock Update
DIR0Counter Direction

CTRLBSETControl B Set

Address
0x42001805
Reset
0x00
Access
read/write
  1. 7CMD2
  2. 6CMD1
  3. 5CMD0
  4. 4IDXCMD1
  5. 3IDXCMD0
  6. 2ONESHOT
  7. 1LUPD
  8. 0DIR
5 fields
FieldBitsWhat it does
CMD7:5TCC Command
  • 0 No action
  • 1 Force start, restart or retrigger
  • 2 Force stop
  • 3 Force update of double buffered registers
  • 4 Force a read synchronization of COUNT
  • 5 One-shot DMA trigger
IDXCMD4:3Ramp Index Command
  • 0 Command disabled: IDX toggles between cycles A and B
  • 1 Set IDX: Cycle B will be forced in the next cycle
  • 2 Clear IDX: Cycle A will be forced in next cycle
  • 3 Hold IDX: The next cycle will be the same as the current cycle
ONESHOT2One-Shot
LUPD1Lock Update
DIR0Counter Direction

SYNCBUSYSynchronization Busy

Address
0x42001808
Reset
0x00000000
Access
read only
Size
32-bit
12 fields
FieldBitsWhat it does
CC311Compare/Capture Channel 3 Synchronization Busy
CC210Compare/Capture Channel 2 Synchronization Busy
CC19Compare/Capture Channel 1 Synchronization Busy
CC08Compare/Capture Channel 0 Synchronization Busy
PER7PER Synchronization Busy
WAVE6WAVE Synchronization Busy
PATT5PATT Synchronization Busy
COUNT4COUNT Synchronization Busy
STATUS3STATUS Synchronization Busy
CTRLB2CTRLB Synchronization Busy
ENABLE1ENABLE Synchronization Busy
SWRST0SWRST Synchronization Busy

FCTRLARecoverable Fault Control #

Address
0x4200180C
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
FILTERVAL27:24Recoverable Fault Filter Value
BLANKVAL23:16Recoverable Fault Blanking Value
BLANKPRESC15Recoverable Fault Blanking Value Prescaler
CAPTURE14:12Recoverable Fault Capture Action
  • 0 Capture on valid recoverable Fault is disabled
  • 1 On the rising edge of a valid recoverable fault, the counter value is captured on the channel selected by CHSEL[1:0]The INTFLAG.FAULTn flag is set on each new captured value.
  • 2 On the rising edge of a valid recoverable fault, the counter value is captured on the channel selected by CHSEL[1:0] if the COUNT value is lower than the last stored capture value (CC).The INTFLAG.FAULTn flag is set on each local minimum detection.
  • 3 On the rising edge of a valid recoverable fault, the counter value is captured on the channel selected by CHSEL[1:0] if the COUNT value is higher than the last stored capture value (CC).The INTFLAG.FAULTn flag is set on each local maximun detection.
  • 4 On the rising edge of a valid recoverable fault, the counter value is captured on the channel selected by CHSEL[1:0].The INTFLAG.FAULTn flag is set on each local minimum value detection.
  • 5 On the rising edge of a valid recoverable fault, the counter value is captured on the channel selected by CHSEL[1:0].The INTFLAG.FAULTn flag is set on each local maximun detection.
  • 6 On the rising edge of a valid recoverable fault, the counter value is captured on the channel selected by CHSEL[1:0].The INTFLAG.FAULTn flag is set on each local maximun or minimum detection.
  • 7 Capture with the ramp index as the MSB value
CHSEL11:10Recoverable Fault Capture Channel
  • 0 The captured value stored in CC0
  • 1 The captured value stored in CC1
  • 2 The captured value stored in CC2
  • 3 The captured value stored in CC3
HALT9:8Recoverable Fault Halt Operation
  • 0 Halt action disabled
  • 1 Hardware halt action
  • 2 Software halt action
  • 3 Non-recoverable fault
RESTART7Recoverable Fault Restart
BLANK6:5Recoverable Fault Blanking Operation
  • 0 Blanking is applied from the start of the ramp period
  • 1 Blanking is applied from the rising edge of the waveform output
  • 2 Blanking is applied from the falling edge of the waveform output
  • 3 Blanking is applied from each toggle of the waveform output
QUAL4Recoverable Fault Qualification
KEEP3Recoverable Fault Keep
SRC1:0Recoverable Fault Source
  • 0 Fault input disabled
  • 1 MCEn (n = 0,1) event input
  • 2 Inverted MCEn (n = 0,1) event input
  • 3 Alternate fault (A or B) state at the end of the previous period.

FCTRLBRecoverable Fault Control #

Address
0x42001810
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
FieldBitsWhat it does
FILTERVAL27:24Recoverable Fault Filter Value
BLANKVAL23:16Recoverable Fault Blanking Value
BLANKPRESC15Recoverable Fault Blanking Value Prescaler
CAPTURE14:12Recoverable Fault Capture Action
  • 0 Capture on valid recoverable Fault is disabled
  • 1 On the rising edge of a valid recoverable fault, the counter value is captured on the channel selected by CHSEL[1:0]The INTFLAG.FAULTn flag is set on each new captured value.
  • 2 On the rising edge of a valid recoverable fault, the counter value is captured on the channel selected by CHSEL[1:0] if the COUNT value is lower than the last stored capture value (CC).The INTFLAG.FAULTn flag is set on each local minimum detection.
  • 3 On the rising edge of a valid recoverable fault, the counter value is captured on the channel selected by CHSEL[1:0] if the COUNT value is higher than the last stored capture value (CC).The INTFLAG.FAULTn flag is set on each local maximun detection.
  • 4 On the rising edge of a valid recoverable fault, the counter value is captured on the channel selected by CHSEL[1:0].The INTFLAG.FAULTn flag is set on each local minimum value detection.
  • 5 On the rising edge of a valid recoverable fault, the counter value is captured on the channel selected by CHSEL[1:0].The INTFLAG.FAULTn flag is set on each local maximun detection.
  • 6 On the rising edge of a valid recoverable fault, the counter value is captured on the channel selected by CHSEL[1:0].The INTFLAG.FAULTn flag is set on each local maximun or minimum detection.
  • 7 Capture with the ramp index as the MSB value
CHSEL11:10Recoverable Fault Capture Channel
  • 0 The captured value stored in CC0
  • 1 The captured value stored in CC1
  • 2 The captured value stored in CC2
  • 3 The captured value stored in CC3
HALT9:8Recoverable Fault Halt Operation
  • 0 Halt action disabled
  • 1 Hardware halt action
  • 2 Software halt action
  • 3 Non-recoverable fault
RESTART7Recoverable Fault Restart
BLANK6:5Recoverable Fault Blanking Operation
  • 0 Blanking is applied from the start of the ramp period
  • 1 Blanking is applied from the rising edge of the waveform output
  • 2 Blanking is applied from the falling edge of the waveform output
  • 3 Blanking is applied from each toggle of the waveform output
QUAL4Recoverable Fault Qualification
KEEP3Recoverable Fault Keep
SRC1:0Recoverable Fault Source
  • 0 Fault input disabled
  • 1 MCEn (n = 0,1) event input
  • 2 Inverted MCEn (n = 0,1) event input
  • 3 Alternate fault (A or B) state at the end of the previous period.

WEXCTRLWaveform Extension Control

Address
0x42001814
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
OTMX1:0Output Matrix

DRVCTRLDriver Control

Address
0x42001818
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
FILTERVAL027:24Non-Recoverable Fault Input 0 Filter Value
INVEN319Waveform Output 3 Inversion
INVEN218Waveform Output 2 Inversion
INVEN117Waveform Output 1 Inversion
INVEN016Waveform Output 0 Inversion
NRV311Non-Recoverable State 3 Output Value
NRV210Non-Recoverable State 2 Output Value
NRV19Non-Recoverable State 1 Output Value
NRV08Non-Recoverable State 0 Output Value
NRE33Non-Recoverable State 3 Output Enable
NRE22Non-Recoverable State 2 Output Enable
NRE11Non-Recoverable State 1 Output Enable
NRE00Non-Recoverable State 0 Output Enable
FILTERVAL131:28Non-Recoverable Fault Input 1 Filter Value

DBGCTRLDebug control

Address
0x4200181E
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2FDDBD
  7. 1–
  8. 0DBGRUN
2 fields
FieldBitsWhat it does
FDDBD2Fault Detection on Debug Break Detection
DBGRUN0Debug Running State

EVCTRLEvent Control

Address
0x42001820
Reset
0x00000000
Access
read/write
Size
32-bit
18 fields
FieldBitsWhat it does
MCEO327Match or Capture Channel 3 Event Output Enable
MCEO226Match or Capture Channel 2 Event Output Enable
MCEO125Match or Capture Channel 1 Event Output Enable
MCEO024Match or Capture Channel 0 Event Output Enable
MCEI319Match or Capture Channel 3 Event Input Enable
MCEI218Match or Capture Channel 2 Event Input Enable
MCEI117Match or Capture Channel 1 Event Input Enable
MCEI016Match or Capture Channel 0 Event Input Enable
TCEI115Timer/Counter Event Input 1 Enable
TCEI014Timer/Counter Event Input 0 Enable
TCINV113Timer/Counter Event 1 Invert Enable
TCINV012Timer/Counter Event 0 Invert Enable
CNTEO10Timer/Counter Event Output Enable
TRGEO9Retrigger Event Output Enable
OVFEO8Overflow/Underflow Event Output Enable
CNTSEL7:6Timer/Counter Interrupt and Event Output Selection
  • 0 An interrupt/event is generated at the beginning of each counter cycle
  • 1 An interrupt/event is generated at the end of each counter cycle
  • 3 An interrupt/event is generated at the beginning of the first counter cycle, and at the end of last counter cycle
EVACT15:3Timer/Counter Event Input 1 Action
  • 0 Event action disabled
  • 1 Restart or retrigger TCC on event
  • 2 Direction control
  • 3 Stop TCC on event
  • 4 Decrement TCC on event
  • 6 Period captured into CC1 Pulse Width on CC0
  • 7 Non-recoverable fault
EVACT02:0Timer/Counter Event Input 0 Action
  • 0 Event action disabled
  • 1 Restart or retrigger TCC on event
  • 2 Count on event
  • 3 Start TCC on event
  • 4 Increment TCC on event
  • 5 Count on the active state of an asynchronous event
  • 6 Capture Time-stamp (overflow)
  • 7 Non-recoverable fault

INTENCLRInterrupt Enable Clear

Address
0x42001824
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
MC319Match or Capture Channel 3 Interrupt Enable
MC218Match or Capture Channel 2 Interrupt Enable
MC117Match or Capture Channel 1 Interrupt Enable
MC016Match or Capture Channel 0 Interrupt Enable
FAULT115Non-Recoverable Fault 1 Interrupt Enable
FAULT014Non-Recoverable Fault 0 Interrupt Enable
FAULTB13Recoverable Fault B Interrupt Enable
FAULTA12Recoverable Fault A Interrupt Enable
DFS11Non-Recoverable Debug Fault Interrupt Enable
UFS10Non-Recoverable Update Fault Interrupt Enable
ERR3Error Interrupt Enable
CNT2Counter Interrupt Enable
TRG1Retrigger Interrupt Enable
OVF0Overflow Interrupt Enable

INTENSETInterrupt Enable Set

Address
0x42001828
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
MC319Match or Capture Channel 3 Interrupt Enable
MC218Match or Capture Channel 2 Interrupt Enable
MC117Match or Capture Channel 1 Interrupt Enable
MC016Match or Capture Channel 0 Interrupt Enable
FAULT115Non-Recoverable Fault 1 Interrupt Enable
FAULT014Non-Recoverable Fault 0 Interrupt Enable
FAULTB13Recoverable Fault B Interrupt Enable
FAULTA12Recoverable Fault A Interrupt Enable
DFS11Non-Recoverable Debug Fault Interrupt Enable
UFS10Non-Recoverable Update Fault Interrupt Enable
ERR3Error Interrupt Enable
CNT2Counter Interrupt Enable
TRG1Retrigger Interrupt Enable
OVF0Overflow Interrupt Enable

INTFLAGInterrupt Flag Status and Clear

Address
0x4200182C
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
MC319Match or Capture Channel 3 Interrupt Flag
MC218Match or Capture Channel 2 Interrupt Flag
MC117Match or Capture Channel 1 Interrupt Flag
MC016Match or Capture Channel 0 Interrupt Flag
FAULT115Non-Recoverable Fault 1 Interrupt Flag
FAULT014Non-Recoverable Fault 0 Interrupt Flag
FAULTB13Recoverable Fault B Interrupt Flag
FAULTA12Recoverable Fault A Interrupt Flag
DFS11Non-Recoverable Debug Fault State Interrupt Flag
UFS10Non-Recoverable Update Fault
ERR3Error Interrupt Flag
CNT2Counter Interrupt Flag
TRG1Retrigger Interrupt Flag
OVF0Overflow Interrupt Flag

STATUSStatus

Address
0x42001830
Reset
0x00000001
Access
read/write
Size
32-bit
22 fields
FieldBitsWhat it does
CMP327Compare Channel 3 Value
CMP226Compare Channel 2 Value
CMP125Compare Channel 1 Value
CMP024Compare Channel 0 Value
CCBUFV319Compare/Capture Channel 3 Buffer Valid
CCBUFV218Compare/Capture Channel 2 Buffer Valid
CCBUFV117Compare/Capture Channel 1 Buffer Valid
CCBUFV016Compare/Capture Channel 0 Buffer Valid
FAULT115Non-recoverable Fault 1 State
FAULT014Non-recoverable Fault 0 State
FAULTB13Recoverable Fault B State
FAULTA12Recoverable Fault A State
FAULT1IN11Non-Recoverable Fault 1 Input
FAULT0IN10Non-Recoverable Fault 0 Input
FAULTBIN9Recoverable Fault B Input
FAULTAIN8Recoverable Fault A Input
PERBUFV7Period Buffer Valid
PATTBUFV5Pattern Generator Value Buffer Valid
DFS3Debug Fault State
UFS2Non-recoverable Update Fault State
IDX1Ramp Index
STOP0Stop

COUNTCounter

Address
0x42001834
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
COUNT15:0Counter Value

PATTPattern

Address
0x42001838
Reset
0x0000
Access
read/write
Size
16-bit
8 fields
FieldBitsWhat it does
PGV311Pattern Generation Output 3 Value
PGV210Pattern Generation Output 2 Value
PGV19Pattern Generation Output 1 Value
PGV08Pattern Generation Output 0 Value
PGE33Pattern Generation Output 3 Enable
PGE22Pattern Generation Output 2 Enable
PGE11Pattern Generation Output 1 Enable
PGE00Pattern Generation Output 0 Enable

WAVEWaveform

Address
0x4200183C
Reset
0x00000000
Access
read/write
Size
32-bit
19 fields
FieldBitsWhat it does
POL319Channel 3 Polarity
  • 0 Compare output is initialized to ~DIR, set to DIR when TCC counter matches CCn value and set to ~DIR when TCC counter matches CC[n+WO_NUM/2] value.
  • 1 Compare output is initialized to DIR, set to ~DIR when TCC counter matches CCn value and set to DIR when TCC counter matches CC[n+WO_NUM/2] value.
POL319Channel 3 Polarity
  • 0 Compare output is set to ~DIR when TCC counter matches CCn value
  • 1 Compare output is set to DIR when TCC counter matches CCn value.
POL319Channel 3 Polarity
  • 0 Compare output is initialized to ~DIR and set to DIR when TCC counter matches CCn value.
  • 1 Compare output is initialized to DIR and set to ~DIR when TCC counter matches CCn value.
POL218Channel 2 Polarity
  • 0 Compare output is initialized to ~DIR, set to DIR when TCC counter matches CCn value and set to ~DIR when TCC counter matches CC[n+WO_NUM/2] value.
  • 1 Compare output is initialized to DIR, set to ~DIR when TCC counter matches CCn value and set to DIR when TCC counter matches CC[n+WO_NUM/2] value.
POL218Channel 2 Polarity
  • 0 Compare output is set to ~DIR when TCC counter matches CCn value
  • 1 Compare output is set to DIR when TCC counter matches CCn value.
POL218Channel 2 Polarity
  • 0 Compare output is initialized to ~DIR and set to DIR when TCC counter matches CCn value.
  • 1 Compare output is initialized to DIR and set to ~DIR when TCC counter matches CCn value.
POL117Channel 1 Polarity
  • 0 Compare output is initialized to ~DIR, set to DIR when TCC counter matches CCn value and set to ~DIR when TCC counter matches CC[n+WO_NUM/2] value.
  • 1 Compare output is initialized to DIR, set to ~DIR when TCC counter matches CCn value and set to DIR when TCC counter matches CC[n+WO_NUM/2] value.
POL117Channel 1 Polarity
  • 0 Compare output is set to ~DIR when TCC counter matches CCn value
  • 1 Compare output is set to DIR when TCC counter matches CCn value.
POL117Channel 1 Polarity
  • 0 Compare output is initialized to ~DIR and set to DIR when TCC counter matches CCn value.
  • 1 Compare output is initialized to DIR and set to ~DIR when TCC counter matches CCn value.
POL016Channel 0 Polarity
  • 0 Compare output is initialized to ~DIR, set to DIR when TCC counter matches CCn value and set to ~DIR when TCC counter matches CC[n+WO_NUM/2] value.
  • 1 Compare output is initialized to DIR, set to ~DIR when TCC counter matches CCn value and set to DIR when TCC counter matches CC[n+WO_NUM/2] value.
POL016Channel 0 Polarity
  • 0 Compare output is set to ~DIR when TCC counter matches CCn value
  • 1 Compare output is set to DIR when TCC counter matches CCn value.
POL016Channel 0 Polarity
  • 0 Compare output is initialized to ~DIR and set to DIR when TCC counter matches CCn value.
  • 1 Compare output is initialized to DIR and set to ~DIR when TCC counter matches CCn value.
CICCEN311Circular Compare/Capture Channel 3 Enable
CICCEN210Circular Compare/Capture Channel 2 Enable
CICCEN19Circular Compare/Capture Channel 1 Enable
CICCEN08Circular Compare/Capture Channel 0 Enable
CIPEREN7Circular Period Enable
RAMP6:4Ramp Operation
  • 0 RAMP1 operation
  • 1 Alternative RAMP2 operation
  • 2 RAMP2 operation
  • 3 Critical RAMP2 operation
WAVEGEN2:0Waveform Generation Operation
  • 0 Normal Frequency
  • 1 Match Frequency
  • 2 Normal PWM
  • 3 Dual Compare PWM
  • 4 Dual-slope PWM
  • 5 Dual-slope PWM
  • 6 Dual-slope PWM
  • 7 Dual-slope PWM

PERPeriod

Address
0x42001840
Reset
0xFFFFFFFF
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
PER15:0Period Value

CC0Compare/Capture Channel #

Address
0x42001844
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CC15:0Compare/Capture Channel Value

CC1Compare/Capture Channel #

Address
0x42001848
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CC15:0Compare/Capture Channel Value

CC2Compare/Capture Channel #

Address
0x4200184C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CC15:0Compare/Capture Channel Value

CC3Compare/Capture Channel #

Address
0x42001850
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CC15:0Compare/Capture Channel Value

PATTBUFPattern Buffer

Address
0x42001864
Reset
0x0000
Access
read/write
Size
16-bit
8 fields
FieldBitsWhat it does
PGVB311Pattern Generation Output Value Buffer 3
PGVB210Pattern Generation Output Value Buffer 2
PGVB19Pattern Generation Output Value Buffer 1
PGVB08Pattern Generation Output Value Buffer 0
PGEB33Pattern Generation Output Enable Buffer 3
PGEB22Pattern Generation Output Enable Buffer 2
PGEB11Pattern Generation Output Enable Buffer 1
PGEB00Pattern Generation Output Enable Buffer 0

PERBUFPeriod Buffer

Address
0x4200186C
Reset
0xFFFFFFFF
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
PERBUF15:0Period Buffer Value

CCBUF0Compare/Capture Channel # Buffer

Address
0x42001870
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CCBUF15:0Compare/Capture Channel Buffer Value

CCBUF1Compare/Capture Channel # Buffer

Address
0x42001874
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CCBUF15:0Compare/Capture Channel Buffer Value

CCBUF2Compare/Capture Channel # Buffer

Address
0x42001878
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CCBUF15:0Compare/Capture Channel Buffer Value

CCBUF3Compare/Capture Channel # Buffer

Address
0x4200187C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CCBUF15:0Compare/Capture Channel Buffer Value