PIC32CM1216PL10064 MCLK registers The 8 registers of MCLK (Main Clock), from 0x40000801, with their reset value and every field. The PIC32CM1216PL10064 has 702 registers in 32 peripherals, one page each.
MCLK Main Clock INTENCLRInterrupt Enable Clear
Address 0x40000801
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CKRDY 1 field
Field Bits What it does CKRDY 0 Clock Ready Interrupt Enable
INTENSETInterrupt Enable Set
Address 0x40000802
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CKRDY 1 field
Field Bits What it does CKRDY 0 Clock Ready Interrupt Enable
INTFLAGInterrupt Flag Status and Clear
Address 0x40000803
Reset 0x01
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CKRDY 1 field
Field Bits What it does CKRDY 0 Clock Ready Interrupt Flag
CPUDIVCPU Clock Division
Address 0x40000804
Reset 0x01
Access read/write 7 CPUDIV7 6 CPUDIV6 5 CPUDIV5 4 CPUDIV4 3 CPUDIV3 2 CPUDIV2 1 CPUDIV1 0 CPUDIV0 1 field
Field Bits What it does CPUDIV 7:0 CPU Clock Division Factor1 Divide by 12 Divide by 24 Divide by 48 Divide by 816 Divide by 1632 Divide by 3264 Divide by 64128 Divide by 128
AHBMASKAHB Bridge Mask
Address 0x40000810
Reset 0x000003FF
Access read/write
Size 32-bit 10 fields
Field Bits What it does BROM_ 9 BROM AHB Clock Mask PAC_ 8 PAC AHB Clock Mask DMAC_ 7 DMAC AHB Clock Mask HSRAM_ 6 HSRAM AHB Clock Mask NVMCTRL_ 5 NVMCTRL AHB Clock Mask HMATRIXHS_ 4 HMATRIXHS AHB Clock Mask DSU_ 3 DSU AHB Clock Mask APBC_ 2 APBC AHB Clock Mask APBB_ 1 APBB AHB Clock Mask APBA_ 0 APBA AHB Clock Mask
APBAMASKAPB Bridge A Mask
Address 0x40000814
Reset 0x000007FF
Access read/write
Size 32-bit 11 fields
Field Bits What it does EIC_ 10 EIC APB Clock Enable RTC_ 9 RTC APB Clock Enable WDT_ 8 WDT APB Clock Enable GCLK_ 7 GCLK APB Clock Enable SUPC_ 6 SUPC APB Clock Enable OSC32KCTRL_ 5 OSC32KCTRL APB Clock Enable OSCCTRL_ 4 OSCCTRL APB Clock Enable RSTC_ 3 RSTC APB Clock Enable MCLK_ 2 MCLK APB Clock Enable PM_ 1 PM APB Clock Enable PAC_ 0 PAC APB Clock Enable
APBBMASKAPB Bridge B Mask
Address 0x40000818
Reset 0x00000027
Access read/write
Size 32-bit 4 fields
Field Bits What it does HMATRIXHS_ 5 HMATRIXHS APB Clock Enable NVMCTRL_ 2 NVMCTRL APB Clock Enable DSU_ 1 DSU APB Clock Enable PORT_ 0 PORT APB Clock Enable
APBCMASKAPB Bridge C Mask
Address 0x4000081C
Reset 0x00000800
Access read/write
Size 32-bit 12 fields
Field Bits What it does SYSCTRL_ 11 SYSCTRL APB Clock Enable PTC_ 10 PTC APB Clock Enable CCL_ 9 CCL APB Clock Enable AC_ 8 AC APB Clock Enable ADC0_ 7 ADC0 APB Clock Enable TCC0_ 6 TCC0 APB Clock Enable TC2_ 5 TC2 APB Clock Enable TC1_ 4 TC1 APB Clock Enable TC0_ 3 TC0 APB Clock Enable SERCOM1_ 2 SERCOM1 APB Clock Enable SERCOM0_ 1 SERCOM0 APB Clock Enable EVSYS_ 0 EVSYS APB Clock Enable