PIC32CM2532JH00048 NVMCTRL registers

The 19 registers of NVMCTRL (Non-Volatile Memory Controller), from 0x41004000, with their reset value and every field. The PIC32CM2532JH00048 has 1227 registers in 49 peripherals, one page each.

NVMCTRL Non-Volatile Memory Controller

CTRLAControl A

Address
0x41004000
Reset
0x0000
Access
read/write
Size
16-bit
2 fields
FieldBitsWhat it does
CMDEX15:8Command Execution
  • 165 Execution Key
CMD6:0Command
  • 2 Erase Row - Erases the row addressed by the ADDR register.
  • 4 Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.
  • 5 Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.
  • 6 Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row.
  • 26 Data Flash Erase Row - Erases the row addressed by the ADDR register.
  • 28 Data Flash Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.
  • 64 Lock Region - Locks the region containing the address location in the ADDR register.
  • 65 Unlock Region - Unlocks the region containing the address location in the ADDR register.
  • 66 Sets the power reduction mode.
  • 67 Clears the power reduction mode.
  • 68 Page Buffer Clear - Clears the page buffer.
  • 69 Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row.
  • 70 Invalidate all cache lines.
  • 127 Set Chip Erase Hard Lock (SCEHL) flash controller command

CTRLBControl B

Address
0x41004004
Reset
0x00000080
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
CACHEDIS19:18Cache Disable
  • 0 The Data Flash cache is disabled, the main array cache is enabled
  • 1 The Data Flash cache is disabled, the main array cache is disabled
  • 2 The Data Flash cache is enabled, the main array cache is enabled
  • 3 The Data Flash cache is enabled, the main array cache is disabled
READMODE17:16NVM Read Mode
  • 0 The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.
  • 1 Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.
  • 2 The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings.
SLEEPPRM9:8Power Reduction Mode during Sleep
  • 0 NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access.
  • 1 NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep.
  • 3 Auto power reduction disabled.
MANW7Manual Write
RWS4:1NVM Read Wait States
  • 0 Single Auto Wait State
  • 1 Half Auto Wait State
  • 2 Dual Auto Wait State

PARAMNVM Parameter

Address
0x41004008
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
PSZ18:16Page Size
  • 0 8 bytes
  • 1 16 bytes
  • 2 32 bytes
  • 3 64 bytes
  • 4 128 bytes
  • 5 256 bytes
  • 6 512 bytes
  • 7 1024 bytes
NVMP15:0NVM Pages
DFP31:20Data Flash Pages

INTENCLRInterrupt Enable Clear

Address
0x4100400C
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
FLTCAP24Fault Capture interrupt enable bit Disable
DERR9Double Bit Error Detection Flag bit Disable
SERR8Single Bit Error Detection Flag bit Disable
ERROR1Error Interrupt Enable
READY0NVM Ready Interrupt Enable

INTENSETInterrupt Enable Set

Address
0x41004010
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
FLTCAP24Fault Capture interrupt enable bit Enable
DERR9Double Bit Error Detection Flag bit Enable
SERR8Single Bit Error Detection Flag bit Enable
ERROR1Error Interrupt Enable
READY0NVM Ready Interrupt Enable

INTFLAGInterrupt Flag Status and Clear

Address
0x41004014
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
FLTCAP24Fault Capture Interrupt
FLASHERR11FLASH Err
DERR9Double bit Error detection flag
SERR8Single Bit Error Detection Flag
ERROR1Error
  • 0 No errors have been received since the last clear
  • 1 At least one error has occurred since the last clear
READY0NVM Ready
  • 0 The NVM controller is busy programming or erasing.
  • 1 The NVM controller is ready to accept a new command

STATUSStatus

Address
0x41004018
Reset
0x0000
Access
read/write
Size
16-bit
6 fields
FieldBitsWhat it does
SB8Security Bit Status
NVME4NVM Error
LOCKE3Lock Error Status
PROGE2Programming Error Status
LOAD1NVM Page Buffer Active Loading
PRM0Power Reduction Mode

ADDRAddress

Address
0x4100401C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADDR21:0NVM Address

LOCKLock Section

Address
0x41004020
Reset
0x0000
Access
read/write
Size
16-bit
1 field
FieldBitsWhat it does
LOCK15:0Region Lock Bits

PBLDATA0Page Buffer Load Data 0

Address
0x41004028
Reset
0xFFFFFFFF
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
PBLDATA31:0Page Buffer Load Data

PBLDATA1Page Buffer Load Data 1

Address
0x4100402C
Reset
0xFFFFFFFF
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
PBLDATA31:0Page Buffer Load Data

ECCCTRLECC control

Address
0x41004080
Reset
0x0000
Access
read/write
Size
16-bit
3 fields
FieldBitsWhat it does
SECCNT15:8Flash SEC Count
ECCDFDIS1Data Flash ECC Disable
  • 0 Data Flash ECC is Enabled
  • 1 Data Flash ECC is Not Enabled, once written to 1 by user ECC can only be re-enabled only by a reset
ECCDIS0FLASH ECC Disable
  • 0 Flash ECC is Enabled
  • 1 Flash ECC is Not Enabled, once written to 1 by user ECC can only be re-enabled only by a reset

FLTCTRLFault injection control

Address
0x41004084
Reset
0x0000
Access
read/write
Size
16-bit
3 fields
FieldBitsWhat it does
FLTMD14:12Fault Mode Control
  • 0 Fault Injection Disabled
  • 2 Fault Capture Mode Enabled (Capture the address (in FFLTCAP) and Syndrome in (FFLTSYND))
  • 4 Single Fault Injection (at bit selected by FLT1PTR) for Reads
  • 5 Double Fault Injection (uses FLT1PTR and FLT2PTR) for Reads
  • 6 Single Fault Injection (at bit selected by FLT1PTR) for Writes
  • 7 Double Fault Injection (uses FLT1PTR and FLT2PTR) for Writes
FLTEN1Fault Injection Enabled
  • 0 Disables the Write/Read fault injection
  • 1 Enables the Write/Read fault injection to occur selected by FLTMD
FLTRST0Fault reset
  • 0 No Effect
  • 1 Resets all FLT SFR bits. {FLTCTRL, FFLTPTR, FFLTADR, FFLTCAP, FFLTPAR, FFLTSYN}

FFLTPTRFault injection pointer

Address
0x41004088
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
FLT2PTR23:16Fault Injection pointer 2
FLT1PTR7:0Fault Injection Pointer 1

FFLTADRFault injection address

Address
0x4100408C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FLTADR23:0Fault Injection Address

FFLTCAPFault error capture addr

Address
0x41004090
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
FLTADR23:0Fault Capture Address

FFLTPARFault parity

Address
0x41004094
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
SECOUT23:16The Calculated Single Error Parity Bits
SECIN7:0Single Error Parity Bits

FFLTSYNFault ECC syndrome

Address
0x41004098
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
DERRSERR17:16Double Error detected, Single error corrected
SECSYN7:0Single Error Syndrome

DBGCTRLDebug control

Address
0x4100409C
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5–
  4. 4–
  5. 3–
  6. 2DBGECC1
  7. 1DBGECC0
  8. 0–
1 field
FieldBitsWhat it does
DBGECC2:1ECC errors from debugger reads are
  • 0 Corrected, INTFLAG is not updated and FLT logic is not updated
  • 1 Not corrected, INTFLAG is not updated, and FLT logic is not updated
  • 2 Corrected, INTFLAG is updated and FLT logic operates as setup
  • 3 Not corrected, INTFLAG is not updated, and FLT logic is not updated