The 43 registers of SERCOM3 (Serial Communication Interface), from 0x42001000, with their reset value and every field. The PIC32CM2532JH01032 has 1128 registers in 48 peripherals, one page each.
SERCOM3 Serial Communication Interface
I2CM.CTRLAI2CM Control A
Address
0x42001000
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
LOWTOUTEN
30
SCL Low Time-Out
INACTOUT
29:28
Inactive Time-Out
0 Disabled
1 5-6 SCL cycle time-out (50-60 us)
2 10-11 SCL cycle time-out (100-110 us)
3 20-21 SCL cycle time-out (200-210 us)
SCLSM
27
SCL Clock Stretch Mode
SPEED
25:24
Transfer Speed
0 Standard-mode (Sm) and Fast-mode (Fm)
1 Fast-mode Plus (Fm+)
SEXTTOEN
23
Client SCL Low Extend Time-Out
MEXTTOEN
22
Host SCL Low Extend Time-Out
SDAHOLD
21:20
SDA Hold Time
0 SDA hold time is disabled
1 SDA hold time is 50-100 ns
2 SDA hold time is 300-600 ns
3 SDA hold time is 400-800 ns
PINOUT
16
Pin Usage
RUNSTDBY
7
Run in Standby
MODE
4:2
Operating Mode
0 USART with external clock
1 USART with internal clock
2 SPI Client mode
3 SPI Host mode
4 I2C Client mode
5 I2C Host mode
ENABLE
1
Enable
SWRST
0
Software Reset
I2CS.CTRLAI2CS Control A
Address
0x42001000
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
Field
Bits
What it does
LOWTOUTEN
30
SCL Low Time-Out
SCLSM
27
SCL Clock Stretch Mode
SPEED
25:24
Transfer Speed
0 Standard-mode (Sm) and Fast-mode (Fm)
1 Fast-mode Plus (Fm+)
SEXTTOEN
23
Client SCL Low Extend Time-Out
SDAHOLD
21:20
SDA Hold Time
0 Disabled
1 50-100 ns hold time
2 300-600 ns hold time
3 400-800 ns hold time
PINOUT
16
Pin Usage
RUNSTDBY
7
Run in Standby
MODE
4:2
Operating Mode
0 USART with external clock
1 USART with internal clock
2 SPI Client mode
3 SPI Host mode
4 I2C Client mode
5 I2C Host mode
ENABLE
1
Enable
SWRST
0
Software Reset
SPI.CTRLASPI Control A
Address
0x42001000
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
DORD
30
Data Order
0 MSb is transferred first
1 LSb is transferred first
CPOL
29
Clock Polarity
0 SCK is low when IDLE. The leading edge of a clock cycle is a rising edge, while the trailing edge is a falling edge.
1 SCK is high when IDLE. The leading edge of a clock cycle is a falling edge, while the trailing edge is a rising edge.
CPHA
28
Clock Phase
0 The data is sampled on a leading SCK edge and changed on a trailing SCK edge
1 The data is sampled on a trailing SCK edge and changed on a leading SCK edge
0 16x over-sampling using arithmetic baud rate generation
1 16x over-sampling using fractional baud rate generation
2 8x over-sampling using arithmetic baud rate generation
3 8x over-sampling using fractional baud rate generation
4 3x over-sampling using arithmetic baud rate generation
IBON
8
Immediate Buffer Overflow Notification
RUNSTDBY
7
Run In Standby
MODE
4:2
Operating Mode
0 USART with external clock
1 USART with internal clock
2 SPI Client mode
3 SPI Host mode
4 I2C Client mode
5 I2C Host mode
ENABLE
1
Enable
SWRST
0
Software Reset
I2CM.CTRLBI2CM Control B
Address
0x42001004
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
ACKACT
18
Acknowledge Action
CMD
17:16
Command
QCEN
9
Quick Command Enable
SMEN
8
Smart Mode Enable
I2CS.CTRLBI2CS Control B
Address
0x42001004
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
ACKACT
18
Acknowledge Action
CMD
17:16
Command
AMODE
15:14
Address Mode
0 The client responds to the address written in ADDR.ADDR masked by the value in ADDR.ADDRMASK. See SERCOM - Serial Communication Interface for additional information.
1 The client responds to the two unique addresses in ADDR.ADDR and ADDR.ADDRMASK
2 The client responds to the range of addresses between and including ADDR.ADDR and ADDR.ADDRMASK. ADDR.ADDR is the upper limit.
AACKEN
10
Automatic Acknowledge Enable
GCMD
9
PMBus Group Command
SMEN
8
Smart Mode Enable
SPI.CTRLBSPI Control B
Address
0x42001004
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
RXEN
17
Receiver Enable
AMODE
15:14
Address Mode
0 ADDRMASK is used as a mask to the ADDR register
1 The client responds to the two unique addresses in ADDR and ADDRMASK
2 The client responds to the range of addresses between and including ADDR and ADDRMASK with ADDR as the upper limit
MSSEN
13
Host SPI Select Enable
SSDE
9
SPI Select Low Detect Enable
PLOADEN
6
Client Data Preload Enable
CHSIZE
2:0
Character Size
0 Eight bits
1 Nine bits
USART.CTRLBUSART Control B
Address
0x42001004
Reset
0x00000000
Access
read/write
Size
32-bit
9 fields
Field
Bits
What it does
LINCMD
25:24
LIN Command
0 Normal USART transmission
1 A break field is transmitted when DATA is written
2 The break, sync, and identifier fields are automatically transmitted when the DATA is written with the identifier
RXEN
17
Receiver Enable
TXEN
16
Transmitter Enable
PMODE
13
Parity Mode
0 Even parity
1 Odd parity
ENC
10
Encoding Format
1 Data is IrDA encoded
SFDE
9
Start of Frame Detection Enable
COLDEN
8
Collision Detection Enable
SBMODE
6
Stop Bit Mode
0 One stop bit
1 Two stop bits
CHSIZE
2:0
Character Size
0 8-bits character
1 9-bits character
5 5-bits character
6 6-bits character
7 7-bits character
USART.CTRLCUSART Control C
Address
0x42001008
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
HDRDLY
11:10
LIN Host Header Delay
0 Delay between break and sync transmission is one bit time. Delay between sync and ID transmission is one bit time.
1 Delay between break and sync transmission is four bit times. Delay between sync and ID transmission is four bit times.
2 Delay between break and sync transmission is eight bit times. Delay between sync and ID transmission is four bit times.
3 Delay between break and sync transmission is 14 bit times. Delay between sync and ID transmission is four bit times.
BRKLEN
9:8
LIN Host Break Length
0 The break field transmission is 13 bit times
1 The break field transmission is 17 bit times
2 The break field transmission is 21 bit times
3 The break field transmission is 26 bit times
GTIME
2:0
Guard Time
I2CM.BAUDI2CM Baud Rate
Address
0x4200100C
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
BAUDLOW
15:8
Host Baud Rate Low
BAUD
7:0
Host Baud Rate
SPI.BAUDSPI Baud Rate
Address
0x4200100C
Reset
0x00
Access
read/write
7BAUD7
6BAUD6
5BAUD5
4BAUD4
3BAUD3
2BAUD2
1BAUD1
0BAUD0
1 field
Field
Bits
What it does
BAUD
7:0
Baud Register
USART.BAUDUSART Baud
Address
0x4200100C
Reset
0x0000
Access
read/write
Size
16-bit
3 fields
Field
Bits
What it does
BAUD
15:0
Baud Value
FP
15:13
Fractional Part
BAUD
12:0
Baud Value
USART.RXPLUSART Receive Pulse Length
Address
0x4200100E
Reset
0x00
Access
read/write
7RXPL7
6RXPL6
5RXPL5
4RXPL4
3RXPL3
2RXPL2
1RXPL1
0RXPL0
1 field
Field
Bits
What it does
RXPL
7:0
Receive Pulse Length
I2CM.INTENCLRI2CM Interrupt Enable Clear
Address
0x42001014
Reset
0x00
Access
read/write
7ERROR
6–
5–
4–
3–
2–
1SB
0MB
3 fields
Field
Bits
What it does
ERROR
7
Error Interrupt Enable
SB
1
Client on Bus Interrupt Enable
MB
0
Host on Bus Interrupt Enable
I2CS.INTENCLRI2CS Interrupt Enable Clear
Address
0x42001014
Reset
0x00
Access
read/write
7ERROR
6–
5–
4–
3–
2DRDY
1AMATCH
0PREC
4 fields
Field
Bits
What it does
ERROR
7
Error Interrupt Enable
DRDY
2
Data Ready Interrupt Enable
AMATCH
1
Address Match Interrupt Enable
PREC
0
Stop Received Interrupt Enable
SPI.INTENCLRSPI Interrupt Enable Clear
Address
0x42001014
Reset
0x00
Access
read/write
7ERROR
6–
5–
4–
3SSL
2RXC
1TXC
0DRE
5 fields
Field
Bits
What it does
ERROR
7
Error Interrupt Enable
SSL
3
SPI Select Low Interrupt Enable
RXC
2
Receive Complete Interrupt Enable
TXC
1
Transmit Complete Interrupt Enable
DRE
0
Data Register Empty Interrupt Enable
USART.INTENCLRUSART Interrupt Enable Clear
Address
0x42001014
Reset
0x00
Access
read/write
7ERROR
6–
5RXBRK
4CTSIC
3RXS
2RXC
1TXC
0DRE
7 fields
Field
Bits
What it does
ERROR
7
Error Interrupt Enable
RXBRK
5
Receive Break Interrupt Enable
CTSIC
4
Clear to Send Input Change Interrupt Enable
RXS
3
Receive Start Interrupt Enable
RXC
2
Receive Complete Interrupt Enable
TXC
1
Transmit Complete Interrupt Enable
DRE
0
Data Register Empty Interrupt Enable
I2CM.INTENSETI2CM Interrupt Enable Set
Address
0x42001016
Reset
0x00
Access
read/write
7ERROR
6–
5–
4–
3–
2–
1SB
0MB
3 fields
Field
Bits
What it does
ERROR
7
Error Interrupt Enable
SB
1
Client on Bus Interrupt Enable
MB
0
Host on Bus Interrupt Enable
I2CS.INTENSETI2CS Interrupt Enable Set
Address
0x42001016
Reset
0x00
Access
read/write
7ERROR
6–
5–
4–
3–
2DRDY
1AMATCH
0PREC
4 fields
Field
Bits
What it does
ERROR
7
Error Interrupt Enable
DRDY
2
Data Ready Interrupt Enable
AMATCH
1
Address Match Interrupt Enable
PREC
0
Stop Received Interrupt Enable
SPI.INTENSETSPI Interrupt Enable Set
Address
0x42001016
Reset
0x00
Access
read/write
7ERROR
6–
5–
4–
3SSL
2RXC
1TXC
0DRE
5 fields
Field
Bits
What it does
ERROR
7
Error Interrupt Enable
SSL
3
SPI Select Low Interrupt Enable
RXC
2
Receive Complete Interrupt Enable
TXC
1
Transmit Complete Interrupt Enable
DRE
0
Data Register Empty Interrupt Enable
USART.INTENSETUSART Interrupt Enable Set
Address
0x42001016
Reset
0x00
Access
read/write
7ERROR
6–
5RXBRK
4CTSIC
3RXS
2RXC
1TXC
0DRE
7 fields
Field
Bits
What it does
ERROR
7
Error Interrupt Enable
RXBRK
5
Receive Break Interrupt Enable
CTSIC
4
Clear to Send Input Change Interrupt Enable
RXS
3
Receive Start Interrupt Enable
RXC
2
Receive Complete Interrupt Enable
TXC
1
Transmit Complete Interrupt Enable
DRE
0
Data Register Empty Interrupt Enable
I2CM.INTFLAGI2CM Interrupt Flag Status and Clear
Address
0x42001018
Reset
0x00
Access
read/write
7ERROR
6–
5–
4–
3–
2–
1SB
0MB
3 fields
Field
Bits
What it does
ERROR
7
Error
SB
1
Client on Bus
MB
0
Host on Bus
I2CS.INTFLAGI2CS Interrupt Flag Status and Clear
Address
0x42001018
Reset
0x00
Access
read/write
7ERROR
6–
5–
4–
3–
2DRDY
1AMATCH
0PREC
4 fields
Field
Bits
What it does
ERROR
7
Error
DRDY
2
Data Ready
AMATCH
1
Address Match
PREC
0
Stop Received
SPI.INTFLAGSPI Interrupt Flag Status and Clear
Address
0x42001018
Reset
0x00
Access
read/write
7ERROR
6–
5–
4–
3SSL
2RXC
1TXC
0DRE
5 fields
Field
Bits
What it does
ERROR
7
Error
SSL
3
SPI Select Low
RXC
2
Receive Complete
TXC
1
Transmit Complete
DRE
0
Data Register Empty
USART.INTFLAGUSART Interrupt Flag Status and Clear
Address
0x42001018
Reset
0x00
Access
read/write
7ERROR
6–
5RXBRK
4CTSIC
3RXS
2RXC
1TXC
0DRE
7 fields
Field
Bits
What it does
ERROR
7
Error
RXBRK
5
Receive Break
CTSIC
4
Clear to Send Input Change
RXS
3
Receive Start
RXC
2
Receive Complete
TXC
1
Transmit Complete
DRE
0
Data Register Empty
I2CM.STATUSI2CM Status
Address
0x4200101A
Reset
0x0000
Access
read/write
Size
16-bit
9 fields
Field
Bits
What it does
LENERR
10
Transaction Length Error
SEXTTOUT
9
Client SCL Low Extend Time-Out
MEXTTOUT
8
Host SCL Low Extend Time-Out
CLKHOLD
7
Clock Hold
LOWTOUT
6
SCL Low Time-Out
BUSSTATE
5:4
Bus State
0 The bus state is unknown to the I2C host, which will wait for a stop condition to be detected or for the bus to be forced into the IDLE state by software
1 The bus state is waiting for a transaction to be initialized