PIC32CM2532LE00100 SERCOM2 registers The 89 registers of SERCOM2 (Serial Communication Interface), from 0x42000C00, with their reset value and every field. The PIC32CM2532LE00100 has 1817 registers in 48 peripherals, one page each.
SERCOM2 Serial Communication Interface I2CM.CTRLAI2CM Control A
Address 0x42000C00
Reset 0x00000000
Access read/write
Size 32-bit 12 fields
Field Bits What it does LOWTOUTEN 30 SCL Low Timeout Enable INACTOUT 29:28 Inactive Time-Out0 Disable1 5-6 SCL cycle time-out2 10-11 SCL cycle time-out3 20-21 SCL cycle time-out SCLSM 27 SCL Clock Stretch Mode SPEED 25:24 Transfer Speed0 Standard-Mode (SM) and Fast-Mode (FM)1 Fast-Mode Plus (FM+)2 High-Speed Mode SEXTTOEN 23 Slave SCL Low Extend Timeout MEXTTOEN 22 Master SCL Low Extend Timeout SDAHOLD 21:20 SDA Hold Time0 Disabled1 50-100ns hold time2 300-600ns hold time3 400-800ns hold time PINOUT 16 Pin Usage RUNSTDBY 7 Run in Standby MODE 4:2 Operating Mode ENABLE 1 Enable SWRST 0 Software Reset
I2CS.CTRLAI2CS Control A
Address 0x42000C00
Reset 0x00000000
Access read/write
Size 32-bit 10 fields
Field Bits What it does LOWTOUTEN 30 SCL Low Timeout Enable SCLSM 27 SCL Clock Stretch Mode SPEED 25:24 Transfer Speed0 Standard-Mode (SM) and Fast-Mode (FM)1 Fast-Mode Plus (FM+)2 High-Speed Mode SEXTTOEN 23 Slave SCL Low Extend Timeout SDAHOLD 21:20 SDA Hold Time0 Disabled1 50-100ns hold time2 300-600ns hold time3 400-800ns hold time PINOUT 16 Pin Usage RUNSTDBY 7 Run during Standby MODE 4:2 Operating Mode ENABLE 1 Enable SWRST 0 Software Reset
SPIM.CTRLASPIM Control A
Address 0x42000C00
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does DORD 30 Data Order0 MSB is transmitted first1 LSB is transmitted first CPOL 29 Clock Polarity0 SCK is low when idle1 SCK is high when idle CPHA 28 Clock Phase0 The data is sampled on a leading SCK edge and changed on a trailing SCK edge1 The data is sampled on a trailing SCK edge and changed on a leading SCK edge FORM 27:24 Frame Format0 SPI Frame2 SPI Frame with Addr DIPO 21:20 Data In Pinout0 SERCOM PAD[0] is used as data input1 SERCOM PAD[1] is used as data input2 SERCOM PAD[2] is used as data input3 SERCOM PAD[3] is used as data input DOPO 17:16 Data Out Pinout0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2]2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] IBON 8 Immediate Buffer Overflow Notification0 STATUS.BUFOVF is set when it occurs in the data stream1 STATUS.BUFOVF is set immediately upon buffer overflow RUNSTDBY 7 Run during Standby MODE 4:2 Operating Mode3 SPI in master operation ENABLE 1 Enable SWRST 0 Software Reset
SPIS.CTRLASPIS Control A
Address 0x42000C00
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does DORD 30 Data Order0 MSB is transmitted first1 LSB is transmitted first CPOL 29 Clock Polarity0 SCK is low when idle1 SCK is high when idle CPHA 28 Clock Phase0 The data is sampled on a leading SCK edge and changed on a trailing SCK edge1 The data is sampled on a trailing SCK edge and changed on a leading SCK edge FORM 27:24 Frame Format0 SPI Frame2 SPI Frame with Addr DIPO 21:20 Data In Pinout0 SERCOM PAD[0] is used as data input1 SERCOM PAD[1] is used as data input2 SERCOM PAD[2] is used as data input3 SERCOM PAD[3] is used as data input DOPO 17:16 Data Out Pinout0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2]2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] IBON 8 Immediate Buffer Overflow Notification0 STATUS.BUFOVF is set when it occurs in the data stream1 STATUS.BUFOVF is set immediately upon buffer overflow RUNSTDBY 7 Run during Standby MODE 4:2 Operating Mode ENABLE 1 Enable SWRST 0 Software Reset
USART_EXT.CTRLAUSART_EXT Control A
Address 0x42000C00
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does DORD 30 Data Order0 MSB is transmitted first.1 LSB is transmitted first. CPOL 29 Clock Polarity0 TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge1 TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge CMODE 28 Communication Mode0 Asynchronous communication.1 Synchronous communication. FORM 27:24 Frame Format0 USART frame1 USART frame with parity2 LIN Master Break and Sync generation4 Auto-baud (LIN Slave) - break detection and auto-baud5 Auto-baud - break detection and auto-baud with parity7 ISO 7816 SAMPA 23:22 Sample Adjustment0 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-51 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-62 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-73 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 RXPO 21:20 Receive Data Pinout0 SERCOM PAD[0] is used for data reception1 SERCOM PAD[1] is used for data reception2 SERCOM PAD[2] is used for data reception3 SERCOM PAD[3] is used for data reception TXPO 17:16 Transmit Data Pinout0 PAD[0] = TxD; PAD[1] = XCK2 PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS3 PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE SAMPR 15:13 Sample0 16x over-sampling using arithmetic baudrate generation1 16x over-sampling using fractional baudrate generation2 8x over-sampling using arithmetic baudrate generation3 8x over-sampling using fractional baudrate generation4 3x over-sampling using arithmetic baudrate generation RXINV 10 Receive Data Invert0 RxD is not inverted1 RxD is inverted TXINV 9 Transmit Data Invert0 TxD is not inverted1 TxD is inverted IBON 8 Immediate Buffer Overflow Notification RUNSTDBY 7 Run during Standby MODE 4:2 Operating Mode0 USART with external clock1 USART with internal clock ENABLE 1 Enable SWRST 0 Software Reset
USART_INT.CTRLAUSART_INT Control A
Address 0x42000C00
Reset 0x00000000
Access read/write
Size 32-bit 15 fields
Field Bits What it does DORD 30 Data Order0 MSB is transmitted first.1 LSB is transmitted first. CPOL 29 Clock Polarity0 TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge1 TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge CMODE 28 Communication Mode0 Asynchronous communication.1 Synchronous communication. FORM 27:24 Frame Format0 USART frame1 USART frame with parity2 LIN Master Break and Sync generation4 Auto-baud (LIN Slave) - break detection and auto-baud5 Auto-baud - break detection and auto-baud with parity7 ISO 7816 SAMPA 23:22 Sample Adjustment0 16x Over-sampling = 7-8-9; 8x Over-sampling = 3-4-51 16x Over-sampling = 9-10-11; 8x Over-sampling = 4-5-62 16x Over-sampling = 11-12-13; 8x Over-sampling = 5-6-73 16x Over-sampling = 13-14-15; 8x Over-sampling = 6-7-8 RXPO 21:20 Receive Data Pinout0 SERCOM PAD[0] is used for data reception1 SERCOM PAD[1] is used for data reception2 SERCOM PAD[2] is used for data reception3 SERCOM PAD[3] is used for data reception TXPO 17:16 Transmit Data Pinout0 PAD[0] = TxD; PAD[1] = XCK2 PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS3 PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE SAMPR 15:13 Sample0 16x over-sampling using arithmetic baudrate generation1 16x over-sampling using fractional baudrate generation2 8x over-sampling using arithmetic baudrate generation3 8x over-sampling using fractional baudrate generation4 3x over-sampling using arithmetic baudrate generation RXINV 10 Receive Data Invert0 RxD is not inverted1 RxD is inverted TXINV 9 Transmit Data Invert0 TxD is not inverted1 TxD is inverted IBON 8 Immediate Buffer Overflow Notification RUNSTDBY 7 Run during Standby MODE 4:2 Operating Mode0 USART with external clock1 USART with internal clock ENABLE 1 Enable SWRST 0 Software Reset
I2CM.CTRLBI2CM Control B
Address 0x42000C04
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does FIFOCLR 23:22 FIFO Clear0 No action1 Clear TX FIFO2 Clear RX FIFO3 Clear both TX and RF FIFOs ACKACT 18 Acknowledge Action CMD 17:16 Command QCEN 9 Quick Command Enable SMEN 8 Smart Mode Enable
I2CS.CTRLBI2CS Control B
Address 0x42000C04
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does FIFOCLR 23:22 FIFO Clear0 No action1 Clear TX FIFO2 Clear RX FIFO3 Clear both TX and RF FIFOs ACKACT 18 Acknowledge Action CMD 17:16 Command AMODE 15:14 Address Mode0 The slave responds to the address written in ADDR.ADDR masked by the value in ADDR.ADDRMASK1 The slave responds to the two unique addresses in ADDR and ADDRMASK2 The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit AACKEN 10 Automatic Address Acknowledge GCMD 9 PMBus Group Command SMEN 8 Smart Mode Enable
SPIM.CTRLBSPIM Control B
Address 0x42000C04
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does FIFOCLR 23:22 FIFO Clear0 No action1 Clear TX FIFO2 Clear RX FIFO3 Clear both TX and RF FIFOs RXEN 17 Receiver Enable AMODE 15:14 Address Mode0 ADDRMASK is used as a mask to the AADR register1 The slave responds to the two unique addresses in ADDR and ADDRMASK2 The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit MSSEN 13 Master Slave Select Enable0 Hardware SS control is disabled1 Hardware SS control is enabled SSDE 9 Slave Select Low Detect Enable0 SS low detector is disabled1 SS low detector is enabled PLOADEN 6 Data Preload Enable CHSIZE 2:0 Character Size
SPIS.CTRLBSPIS Control B
Address 0x42000C04
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does FIFOCLR 23:22 FIFO Clear0 No action1 Clear TX FIFO2 Clear RX FIFO3 Clear both TX and RF FIFOs RXEN 17 Receiver Enable AMODE 15:14 Address Mode0 ADDRMASK is used as a mask to the AADR register1 The slave responds to the two unique addresses in ADDR and ADDRMASK2 The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit MSSEN 13 Master Slave Select Enable0 Hardware SS control is disabled1 Hardware SS control is enabled SSDE 9 Slave Select Low Detect Enable0 SS low detector is disabled1 SS low detector is enabled PLOADEN 6 Data Preload Enable CHSIZE 2:0 Character Size
USART_EXT.CTRLBUSART_EXT Control B
Address 0x42000C04
Reset 0x00000000
Access read/write
Size 32-bit 10 fields
Field Bits What it does LINCMD 25:24 LIN Command0 Normal USART transmission1 Break field is transmitted when DATA is written2 Break, sync and identifier are automatically transmitted when DATA is written with the identifier FIFOCLR 23:22 FIFO Clear0 No action1 Clear TX FIFO2 Clear RX FIFO3 Clear both TX and RF FIFOs RXEN 17 Receiver Enable TXEN 16 Transmitter Enable PMODE 13 Parity Mode0 Even Parity1 Odd Parity ENC 10 Encoding Format0 Data is not encoded1 Data is IrDA encoded SFDE 9 Start of Frame Detection Enable COLDEN 8 Collision Detection Enable SBMODE 6 Stop Bit Mode0 One Stop Bit1 Two Stop Bits CHSIZE 2:0 Character Size0 8 Bits1 9 Bits5 5 Bits6 6 Bits7 7 Bits
USART_INT.CTRLBUSART_INT Control B
Address 0x42000C04
Reset 0x00000000
Access read/write
Size 32-bit 10 fields
Field Bits What it does LINCMD 25:24 LIN Command0 Normal USART transmission1 Break field is transmitted when DATA is written2 Break, sync and identifier are automatically transmitted when DATA is written with the identifier FIFOCLR 23:22 FIFO Clear0 No action1 Clear TX FIFO2 Clear RX FIFO3 Clear both TX and RF FIFOs RXEN 17 Receiver Enable TXEN 16 Transmitter Enable PMODE 13 Parity Mode0 Even Parity1 Odd Parity ENC 10 Encoding Format0 Data is not encoded1 Data is IrDA encoded SFDE 9 Start of Frame Detection Enable COLDEN 8 Collision Detection Enable SBMODE 6 Stop Bit Mode0 One Stop Bit1 Two Stop Bits CHSIZE 2:0 Character Size0 8 Bits1 9 Bits5 5 Bits6 6 Bits7 7 Bits
I2CM.CTRLCI2CM Control C
Address 0x42000C08
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RXTRHOLD 29:28 Receive FIFO Threshold0 Interrupt and DMA triggers are generated when DATA is present in the FIFO1 Interrupt and DMA triggers are generated when FIFO is half-full2 Interrupt and DMA triggers are generated when FIFO is full FIFOEN 27 FIFO Enable DATA32B 24 Data 32 Bit TXTRHOLD 31:30 Transmit FIFO Threshold0 Interrupt and DMA triggers are generated as long as the FIFO is not full1 Interrupt and DMA triggers are generated when half FIFO space is free2 Interrupt and DMA triggers are generated as long as the FIFO is not full
I2CS.CTRLCI2CS Control C
Address 0x42000C08
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does RXTRHOLD 29:28 Receive FIFO Threshold0 Interrupt and DMA triggers are generated when DATA is present in the FIFO1 Interrupt and DMA triggers are generated when FIFO is half-full2 Interrupt and DMA triggers are generated when FIFO is full FIFOEN 27 FIFO Enable DATA32B 24 Data 32 Bit SDASETUP 3:0 SDA Setup Time TXTRHOLD 31:30 Transmit FIFO Threshold0 Interrupt and DMA triggers are generated as long as the FIFO is not full1 Interrupt and DMA triggers are generated when half FIFO space is free2 Interrupt and DMA triggers are generated as long as the FIFO is not full
SPIM.CTRLCSPIM Control C
Address 0x42000C08
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does RXTRHOLD 29:28 Receive FIFO Threshold0 Interrupt and DMA triggers are generated when DATA is present in the FIFO1 Interrupt and DMA triggers are generated when FIFO is half-full2 Interrupt and DMA triggers are generated when FIFO is full FIFOEN 27 FIFO Enable DATA32B 24 Data 32 Bit ICSPACE 5:0 Inter-Character Spacing TXTRHOLD 31:30 Transmit FIFO Threshold0 Interrupt and DMA triggers are generated as long as the FIFO is not full1 Interrupt and DMA triggers are generated when half FIFO space is free2 Interrupt and DMA triggers are generated as long as the FIFO is empty
SPIS.CTRLCSPIS Control C
Address 0x42000C08
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does RXTRHOLD 29:28 Receive FIFO Threshold0 Interrupt and DMA triggers are generated when DATA is present in the FIFO1 Interrupt and DMA triggers are generated when FIFO is half-full2 Interrupt and DMA triggers are generated when FIFO is full FIFOEN 27 FIFO Enable DATA32B 24 Data 32 Bit ICSPACE 5:0 Inter-Character Spacing TXTRHOLD 31:30 Transmit FIFO Threshold0 Interrupt and DMA triggers are generated as long as the FIFO is not full1 Interrupt and DMA triggers are generated when half FIFO space is free2 Interrupt and DMA triggers are generated as long as the FIFO is empty
USART_EXT.CTRLCUSART_EXT Control C
Address 0x42000C08
Reset 0x00000000
Access read/write
Size 32-bit 10 fields
Field Bits What it does RXTRHOLD 29:28 Receive FIFO Threshold0 Interrupt and DMA triggers are generated when DATA is present in the FIFO1 Interrupt and DMA triggers are generated when FIFO is half-full2 Interrupt and DMA triggers are generated when FIFO is full FIFOEN 27 FIFO Enable DATA32B 25:24 Data 32 Bit0 Reads and writes with CHSIZE1 Reads with CHSIZE, writes with 32-bit extension2 Reads with 32-bit extension, writes with CHSIZE3 Reads and writes with 32-bit extension MAXITER 22:20 Maximum Iterations DSNACK 17 Disable Successive NACK INACK 16 Inhibit Not Acknowledge HDRDLY 11:10 LIN Master Header Delay0 Delay between break and sync transmission is 1 bit time; Delay between sync and ID transmission is 1 bit time1 Delay between break and sync transmission is 4 bit time; Delay between sync and ID transmission is 4 bit time2 Delay between break and sync transmission is 8 bit time; Delay between sync and ID transmission is 4 bit time3 Delay between break and sync transmission is 14 bit time; Delay between sync and ID transmission is 4 bit time BRKLEN 9:8 LIN Master Break Length0 Break field transmission is 13 bit times1 Break field transmission is 17 bit times2 Break field transmission is 21 bit times3 Break field transmission is 26 bit times GTIME 2:0 Guard Time TXTRHOLD 31:30 Transmit FIFO Threshold0 Interrupt and DMA triggers are generated as long as the FIFO is not full1 Interrupt and DMA triggers are generated when half FIFO space is free2 Interrupt and DMA triggers are generated when the FIFO is empty
USART_INT.CTRLCUSART_INT Control C
Address 0x42000C08
Reset 0x00000000
Access read/write
Size 32-bit 10 fields
Field Bits What it does RXTRHOLD 29:28 Receive FIFO Threshold0 Interrupt and DMA triggers are generated when DATA is present in the FIFO1 Interrupt and DMA triggers are generated when FIFO is half-full2 Interrupt and DMA triggers are generated when FIFO is full FIFOEN 27 FIFO Enable DATA32B 25:24 Data 32 Bit0 Reads and writes with CHSIZE1 Reads with CHSIZE, writes with 32-bit extension2 Reads with 32-bit extension, writes with CHSIZE3 Reads and writes with 32-bit extension MAXITER 22:20 Maximum Iterations DSNACK 17 Disable Successive NACK INACK 16 Inhibit Not Acknowledge HDRDLY 11:10 LIN Master Header Delay0 Delay between break and sync transmission is 1 bit time; Delay between sync and ID transmission is 1 bit time1 Delay between break and sync transmission is 4 bit time; Delay between sync and ID transmission is 4 bit time2 Delay between break and sync transmission is 8 bit time; Delay between sync and ID transmission is 4 bit time3 Delay between break and sync transmission is 14 bit time; Delay between sync and ID transmission is 4 bit time BRKLEN 9:8 LIN Master Break Length0 Break field transmission is 13 bit times1 Break field transmission is 17 bit times2 Break field transmission is 21 bit times3 Break field transmission is 26 bit times GTIME 2:0 Guard Time TXTRHOLD 31:30 Transmit FIFO Threshold0 Interrupt and DMA triggers are generated as long as the FIFO is not full1 Interrupt and DMA triggers are generated when half FIFO space is free2 Interrupt and DMA triggers are generated when the FIFO is empty
I2CM.BAUDI2CM Baud Rate
Address 0x42000C0C
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does HSBAUD 23:16 High Speed Baud Rate Value BAUDLOW 15:8 Baud Rate Value Low BAUD 7:0 Baud Rate Value HSBAUDLOW 31:24 High Speed Baud Rate Value Low
SPIM.BAUDSPIM Baud Rate
Address 0x42000C0C
Reset 0x00
Access read/write 7 BAUD7 6 BAUD6 5 BAUD5 4 BAUD4 3 BAUD3 2 BAUD2 1 BAUD1 0 BAUD0 1 field
Field Bits What it does BAUD 7:0 Baud Rate Value
SPIS.BAUDSPIS Baud Rate
Address 0x42000C0C
Reset 0x00
Access read/write 7 BAUD7 6 BAUD6 5 BAUD5 4 BAUD4 3 BAUD3 2 BAUD2 1 BAUD1 0 BAUD0 1 field
Field Bits What it does BAUD 7:0 Baud Rate Value
USART_EXT.BAUDUSART_EXT Baud Rate
Address 0x42000C0C
Reset 0x0000
Access read/write
Size 16-bit 3 fields
Field Bits What it does BAUD 15:0 Baud Rate Value FP 15:13 Fractional Part BAUD 12:0 Baud Rate Value
USART_INT.BAUDUSART_INT Baud Rate
Address 0x42000C0C
Reset 0x0000
Access read/write
Size 16-bit 3 fields
Field Bits What it does BAUD 15:0 Baud Rate Value FP 15:13 Fractional Part BAUD 12:0 Baud Rate Value
USART_EXT.RXPLUSART_EXT Receive Pulse Length
Address 0x42000C0E
Reset 0x00
Access read/write 7 RXPL7 6 RXPL6 5 RXPL5 4 RXPL4 3 RXPL3 2 RXPL2 1 RXPL1 0 RXPL0 1 field
Field Bits What it does RXPL 7:0 Receive Pulse Length
USART_INT.RXPLUSART_INT Receive Pulse Length
Address 0x42000C0E
Reset 0x00
Access read/write 7 RXPL7 6 RXPL6 5 RXPL5 4 RXPL4 3 RXPL3 2 RXPL2 1 RXPL1 0 RXPL0 1 field
Field Bits What it does RXPL 7:0 Receive Pulse Length
I2CM.INTENCLRI2CM Interrupt Enable Clear
Address 0x42000C14
Reset 0x00
Access read/write 7 ERROR 6 – 5 – 4 RXFF 3 TXFE 2 – 1 SB 0 MB 5 fields
Field Bits What it does ERROR 7 Combined Error Interrupt Disable RXFF 4 Rx FIFO Full Interrupt Disable TXFE 3 Tx FIFO Empty Interrupt Disable SB 1 Slave On Bus Interrupt Disable MB 0 Master On Bus Interrupt Disable
I2CS.INTENCLRI2CS Interrupt Enable Clear
Address 0x42000C14
Reset 0x00
Access read/write 7 ERROR 6 – 5 – 4 RXFF 3 TXFE 2 DRDY 1 AMATCH 0 PREC 6 fields
Field Bits What it does ERROR 7 Combined Error Interrupt Disable RXFF 4 Rx FIFO Full Interrupt Disable TXFE 3 Tx FIFO Empty Interrupt Disable DRDY 2 Data Interrupt Disable AMATCH 1 Address Match Interrupt Disable PREC 0 Stop Received Interrupt Disable
SPIM.INTENCLRSPIM Interrupt Enable Clear
Address 0x42000C14
Reset 0x00
Access read/write 7 ERROR 6 – 5 – 4 – 3 SSL 2 RXC 1 TXC 0 DRE 5 fields
Field Bits What it does ERROR 7 Combined Error Interrupt Disable SSL 3 Slave Select Low Interrupt Disable RXC 2 Receive Complete Interrupt Disable TXC 1 Transmit Complete Interrupt Disable DRE 0 Data Register Empty Interrupt Disable
SPIS.INTENCLRSPIS Interrupt Enable Clear
Address 0x42000C14
Reset 0x00
Access read/write 7 ERROR 6 – 5 – 4 – 3 SSL 2 RXC 1 TXC 0 DRE 5 fields
Field Bits What it does ERROR 7 Combined Error Interrupt Disable SSL 3 Slave Select Low Interrupt Disable RXC 2 Receive Complete Interrupt Disable TXC 1 Transmit Complete Interrupt Disable DRE 0 Data Register Empty Interrupt Disable
USART_EXT.INTENCLRUSART_EXT Interrupt Enable Clear
Address 0x42000C14
Reset 0x00
Access read/write 7 ERROR 6 – 5 RXBRK 4 CTSIC 3 RXS 2 RXC 1 TXC 0 DRE 7 fields
Field Bits What it does ERROR 7 Combined Error Interrupt Disable RXBRK 5 Break Received Interrupt Disable CTSIC 4 Clear To Send Input Change Interrupt Disable RXS 3 Receive Start Interrupt Disable RXC 2 Receive Complete Interrupt Disable TXC 1 Transmit Complete Interrupt Disable DRE 0 Data Register Empty Interrupt Disable
USART_INT.INTENCLRUSART_INT Interrupt Enable Clear
Address 0x42000C14
Reset 0x00
Access read/write 7 ERROR 6 – 5 RXBRK 4 CTSIC 3 RXS 2 RXC 1 TXC 0 DRE 7 fields
Field Bits What it does ERROR 7 Combined Error Interrupt Disable RXBRK 5 Break Received Interrupt Disable CTSIC 4 Clear To Send Input Change Interrupt Disable RXS 3 Receive Start Interrupt Disable RXC 2 Receive Complete Interrupt Disable TXC 1 Transmit Complete Interrupt Disable DRE 0 Data Register Empty Interrupt Disable
I2CM.INTENSETI2CM Interrupt Enable Set
Address 0x42000C16
Reset 0x00
Access read/write 7 ERROR 6 – 5 – 4 RXFF 3 TXFE 2 – 1 SB 0 MB 5 fields
Field Bits What it does ERROR 7 Combined Error Interrupt Enable RXFF 4 Rx FIFO Full Interrupt Enable TXFE 3 Tx FIFO Empty Interrupt Enable SB 1 Slave On Bus Interrupt Enable MB 0 Master On Bus Interrupt Enable
I2CS.INTENSETI2CS Interrupt Enable Set
Address 0x42000C16
Reset 0x00
Access read/write 7 ERROR 6 – 5 – 4 RXFF 3 TXFE 2 DRDY 1 AMATCH 0 PREC 6 fields
Field Bits What it does ERROR 7 Combined Error Interrupt Enable RXFF 4 Rx FIFO Full Interrupt Enable TXFE 3 Tx FIFO Empty Interrupt Enable DRDY 2 Data Interrupt Enable AMATCH 1 Address Match Interrupt Enable PREC 0 Stop Received Interrupt Enable
SPIM.INTENSETSPIM Interrupt Enable Set
Address 0x42000C16
Reset 0x00
Access read/write 7 ERROR 6 – 5 – 4 – 3 SSL 2 RXC 1 TXC 0 DRE 5 fields
Field Bits What it does ERROR 7 Combined Error Interrupt Enable SSL 3 Slave Select Low Interrupt Enable RXC 2 Receive Complete Interrupt Enable TXC 1 Transmit Complete Interrupt Enable DRE 0 Data Register Empty Interrupt Enable
SPIS.INTENSETSPIS Interrupt Enable Set
Address 0x42000C16
Reset 0x00
Access read/write 7 ERROR 6 – 5 – 4 – 3 SSL 2 RXC 1 TXC 0 DRE 5 fields
Field Bits What it does ERROR 7 Combined Error Interrupt Enable SSL 3 Slave Select Low Interrupt Enable RXC 2 Receive Complete Interrupt Enable TXC 1 Transmit Complete Interrupt Enable DRE 0 Data Register Empty Interrupt Enable
USART_EXT.INTENSETUSART_EXT Interrupt Enable Set
Address 0x42000C16
Reset 0x00
Access read/write 7 ERROR 6 – 5 RXBRK 4 CTSIC 3 RXS 2 RXC 1 TXC 0 DRE 7 fields
Field Bits What it does ERROR 7 Combined Error Interrupt Enable RXBRK 5 Break Received Interrupt Enable CTSIC 4 Clear To Send Input Change Interrupt Enable RXS 3 Receive Start Interrupt Enable RXC 2 Receive Complete Interrupt Enable TXC 1 Transmit Complete Interrupt Enable DRE 0 Data Register Empty Interrupt Enable
USART_INT.INTENSETUSART_INT Interrupt Enable Set
Address 0x42000C16
Reset 0x00
Access read/write 7 ERROR 6 – 5 RXBRK 4 CTSIC 3 RXS 2 RXC 1 TXC 0 DRE 7 fields
Field Bits What it does ERROR 7 Combined Error Interrupt Enable RXBRK 5 Break Received Interrupt Enable CTSIC 4 Clear To Send Input Change Interrupt Enable RXS 3 Receive Start Interrupt Enable RXC 2 Receive Complete Interrupt Enable TXC 1 Transmit Complete Interrupt Enable DRE 0 Data Register Empty Interrupt Enable
I2CM.INTFLAGI2CM Interrupt Flag Status and Clear
Address 0x42000C18
Reset 0x00
Access read/write 7 ERROR 6 – 5 – 4 RXFF 3 TXFE 2 – 1 SB 0 MB 5 fields
Field Bits What it does ERROR 7 Combined Error Interrupt RXFF 4 Rx FIFO Full Interrupt TXFE 3 Tx FIFO Empty Interrupt SB 1 Slave On Bus Interrupt MB 0 Master On Bus Interrupt
I2CS.INTFLAGI2CS Interrupt Flag Status and Clear
Address 0x42000C18
Reset 0x00
Access read/write 7 ERROR 6 – 5 – 4 RXFF 3 TXFE 2 DRDY 1 AMATCH 0 PREC 6 fields
Field Bits What it does ERROR 7 Combined Error Interrupt RXFF 4 Rx FIFO Full Interrupt TXFE 3 Tx FIFO Empty Interrupt DRDY 2 Data Interrupt AMATCH 1 Address Match Interrupt PREC 0 Stop Received Interrupt
SPIM.INTFLAGSPIM Interrupt Flag Status and Clear
Address 0x42000C18
Reset 0x00
Access read/write 7 ERROR 6 – 5 – 4 – 3 SSL 2 RXC 1 TXC 0 DRE 5 fields
Field Bits What it does ERROR 7 Combined Error Interrupt SSL 3 Slave Select Low Interrupt Flag RXC 2 Receive Complete Interrupt TXC 1 Transmit Complete Interrupt DRE 0 Data Register Empty Interrupt
SPIS.INTFLAGSPIS Interrupt Flag Status and Clear
Address 0x42000C18
Reset 0x00
Access read/write 7 ERROR 6 – 5 – 4 – 3 SSL 2 RXC 1 TXC 0 DRE 5 fields
Field Bits What it does ERROR 7 Combined Error Interrupt SSL 3 Slave Select Low Interrupt Flag RXC 2 Receive Complete Interrupt TXC 1 Transmit Complete Interrupt DRE 0 Data Register Empty Interrupt
USART_EXT.INTFLAGUSART_EXT Interrupt Flag Status and Clear
Address 0x42000C18
Reset 0x00
Access read/write 7 ERROR 6 – 5 RXBRK 4 CTSIC 3 RXS 2 RXC 1 TXC 0 DRE 7 fields
Field Bits What it does ERROR 7 Combined Error Interrupt RXBRK 5 Break Received Interrupt CTSIC 4 Clear To Send Input Change Interrupt RXS 3 Receive Start Interrupt RXC 2 Receive Complete Interrupt TXC 1 Transmit Complete Interrupt DRE 0 Data Register Empty Interrupt
USART_INT.INTFLAGUSART_INT Interrupt Flag Status and Clear
Address 0x42000C18
Reset 0x00
Access read/write 7 ERROR 6 – 5 RXBRK 4 CTSIC 3 RXS 2 RXC 1 TXC 0 DRE 7 fields
Field Bits What it does ERROR 7 Combined Error Interrupt RXBRK 5 Break Received Interrupt CTSIC 4 Clear To Send Input Change Interrupt RXS 3 Receive Start Interrupt RXC 2 Receive Complete Interrupt TXC 1 Transmit Complete Interrupt DRE 0 Data Register Empty Interrupt
I2CM.STATUSI2CM Status
Address 0x42000C1A
Reset 0x0000
Access read/write
Size 16-bit 9 fields
Field Bits What it does LENERR 10 Length Error SEXTTOUT 9 Slave SCL Low Extend Timeout MEXTTOUT 8 Master SCL Low Extend Timeout CLKHOLD 7 Clock Hold LOWTOUT 6 SCL Low Timeout BUSSTATE 5:4 Bus State0 Wait for stop or idle1 Wait for transaction initialization2 I2C master is the current owner of the bus3 Some other I2C master owns the bus RXNACK 2 Received Not Acknowledge ARBLOST 1 Arbitration Lost BUSERR 0 Bus Error
I2CS.STATUSI2CS Status
Address 0x42000C1A
Reset 0x0000
Access read/write
Size 16-bit 10 fields
Field Bits What it does LENERR 11 Transaction Length Error HS 10 High Speed SEXTTOUT 9 Slave SCL Low Extend Timeout CLKHOLD 7 Clock Hold LOWTOUT 6 SCL Low Timeout SR 4 Repeated Start DIR 3 Read/Write Direction RXNACK 2 Received Not Acknowledge COLL 1 Transmit Collision BUSERR 0 Bus Error
SPIM.STATUSSPIM Status
Address 0x42000C1A
Reset 0x0000
Access read/write
Size 16-bit 2 fields
Field Bits What it does LENERR 11 Transaction Length Error BUFOVF 2 Buffer Overflow
SPIS.STATUSSPIS Status
Address 0x42000C1A
Reset 0x0000
Access read/write
Size 16-bit 2 fields
Field Bits What it does LENERR 11 Transaction Length Error BUFOVF 2 Buffer Overflow
USART_EXT.STATUSUSART_EXT Status
Address 0x42000C1A
Reset 0x0000
Access read/write
Size 16-bit 8 fields
Field Bits What it does ITER 7 Maximum Number of Repetitions Reached TXE 6 Transmitter Empty COLL 5 Collision Detected ISF 4 Inconsistent Sync Field CTS 3 Clear To Send BUFOVF 2 Buffer Overflow FERR 1 Frame Error PERR 0 Parity Error
USART_INT.STATUSUSART_INT Status
Address 0x42000C1A
Reset 0x0000
Access read/write
Size 16-bit 8 fields
Field Bits What it does ITER 7 Maximum Number of Repetitions Reached TXE 6 Transmitter Empty COLL 5 Collision Detected ISF 4 Inconsistent Sync Field CTS 3 Clear To Send BUFOVF 2 Buffer Overflow FERR 1 Frame Error PERR 0 Parity Error
I2CM.SYNCBUSYI2CM Synchronization Busy
Address 0x42000C1C
Reset 0x00000000
Access read only
Size 32-bit 3 fields
Field Bits What it does SYSOP 2 System Operation Synchronization Busy ENABLE 1 SERCOM Enable Synchronization Busy SWRST 0 Software Reset Synchronization Busy
I2CS.SYNCBUSYI2CS Synchronization Busy
Address 0x42000C1C
Reset 0x00000000
Access read only
Size 32-bit 4 fields
Field Bits What it does LENGTH 4 Length Synchronization Busy SYSOP 2 System Operation Synchronization Busy ENABLE 1 SERCOM Enable Synchronization Busy SWRST 0 Software Reset Synchronization Busy
SPIM.SYNCBUSYSPIM Synchronization Busy
Address 0x42000C1C
Reset 0x00000000
Access read only
Size 32-bit 4 fields
Field Bits What it does LENGTH 4 LENGTH Synchronization Busy CTRLB 2 CTRLB Synchronization Busy ENABLE 1 SERCOM Enable Synchronization Busy SWRST 0 Software Reset Synchronization Busy
SPIS.SYNCBUSYSPIS Synchronization Busy
Address 0x42000C1C
Reset 0x00000000
Access read only
Size 32-bit 4 fields
Field Bits What it does LENGTH 4 LENGTH Synchronization Busy CTRLB 2 CTRLB Synchronization Busy ENABLE 1 SERCOM Enable Synchronization Busy SWRST 0 Software Reset Synchronization Busy
USART_EXT.SYNCBUSYUSART_EXT Synchronization Busy
Address 0x42000C1C
Reset 0x00000000
Access read only
Size 32-bit 5 fields
Field Bits What it does LENGTH 4 LENGTH Synchronization Busy RXERRCNT 3 RXERRCNT Synchronization Busy CTRLB 2 CTRLB Synchronization Busy ENABLE 1 SERCOM Enable Synchronization Busy SWRST 0 Software Reset Synchronization Busy
USART_INT.SYNCBUSYUSART_INT Synchronization Busy
Address 0x42000C1C
Reset 0x00000000
Access read only
Size 32-bit 5 fields
Field Bits What it does LENGTH 4 LENGTH Synchronization Busy RXERRCNT 3 RXERRCNT Synchronization Busy CTRLB 2 CTRLB Synchronization Busy ENABLE 1 SERCOM Enable Synchronization Busy SWRST 0 Software Reset Synchronization Busy
USART_EXT.RXERRCNTUSART_EXT Receive Error Count
Address 0x42000C20
Reset 0x00
Access read only 7 RXERRCNT7 6 RXERRCNT6 5 RXERRCNT5 4 RXERRCNT4 3 RXERRCNT3 2 RXERRCNT2 1 RXERRCNT1 0 RXERRCNT0 1 field
Field Bits What it does RXERRCNT 7:0 Receive Error Count
USART_INT.RXERRCNTUSART_INT Receive Error Count
Address 0x42000C20
Reset 0x00
Access read only 7 RXERRCNT7 6 RXERRCNT6 5 RXERRCNT5 4 RXERRCNT4 3 RXERRCNT3 2 RXERRCNT2 1 RXERRCNT1 0 RXERRCNT0 1 field
Field Bits What it does RXERRCNT 7:0 Receive Error Count
I2CS.LENGTHI2CS Length
Address 0x42000C22
Reset 0x0000
Access read/write
Size 16-bit 2 fields
Field Bits What it does LENEN 8 Data Length Enable LEN 7:0 Data Length
SPIM.LENGTHSPIM Length
Address 0x42000C22
Reset 0x0000
Access read/write
Size 16-bit 2 fields
Field Bits What it does LENEN 8 Data Length Enable LEN 7:0 Data Length
SPIS.LENGTHSPIS Length
Address 0x42000C22
Reset 0x0000
Access read/write
Size 16-bit 2 fields
Field Bits What it does LENEN 8 Data Length Enable LEN 7:0 Data Length
USART_EXT.LENGTHUSART_EXT Length
Address 0x42000C22
Reset 0x0000
Access read/write
Size 16-bit 2 fields
Field Bits What it does LENEN 9:8 Data Length Enable0 Length counter is disabled1 Length counter is enabled for transmit2 Length counter is enabled for receive LEN 7:0 Data Length
USART_INT.LENGTHUSART_INT Length
Address 0x42000C22
Reset 0x0000
Access read/write
Size 16-bit 2 fields
Field Bits What it does LENEN 9:8 Data Length Enable0 Length counter is disabled1 Length counter is enabled for transmit2 Length counter is enabled for receive LEN 7:0 Data Length
I2CM.ADDRI2CM Address
Address 0x42000C24
Reset 0x00000000
Access read/write
Size 32-bit 5 fields
Field Bits What it does LEN 23:16 Length TENBITEN 15 Ten Bit Addressing Enable HS 14 High Speed Mode LENEN 13 Length Enable ADDR 10:0 Address Value
I2CS.ADDRI2CS Address
Address 0x42000C24
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does ADDRMASK 26:17 Address Mask TENBITEN 15 Ten Bit Addressing Enable ADDR 10:1 Address Value GENCEN 0 General Call Address Enable
SPIM.ADDRSPIM Address
Address 0x42000C24
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does ADDRMASK 23:16 Address Mask ADDR 7:0 Address Value
SPIS.ADDRSPIS Address
Address 0x42000C24
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does ADDRMASK 23:16 Address Mask ADDR 7:0 Address Value
I2CM.DATAI2CM Data
Address 0x42000C28
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DATA 31:0 Data Value
I2CS.DATAI2CS Data
Address 0x42000C28
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DATA 31:0 Data Value
SPIM.DATASPIM Data
Address 0x42000C28
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DATA 31:0 Data Value
SPIS.DATASPIS Data
Address 0x42000C28
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DATA 31:0 Data Value
USART_EXT.DATAUSART_EXT Data
Address 0x42000C28
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DATA 31:0 Data Value
USART_INT.DATAUSART_INT Data
Address 0x42000C28
Reset 0x00000000
Access read/write
Size 32-bit 1 field
Field Bits What it does DATA 31:0 Data Value
I2CM.DBGCTRLI2CM Debug Control
Address 0x42000C30
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 DBGSTOP 1 field
Field Bits What it does DBGSTOP 0 Debug Mode
SPIM.DBGCTRLSPIM Debug Control
Address 0x42000C30
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 DBGSTOP 1 field
Field Bits What it does DBGSTOP 0 Debug Mode
SPIS.DBGCTRLSPIS Debug Control
Address 0x42000C30
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 DBGSTOP 1 field
Field Bits What it does DBGSTOP 0 Debug Mode
USART_EXT.DBGCTRLUSART_EXT Debug Control
Address 0x42000C30
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 DBGSTOP 1 field
Field Bits What it does DBGSTOP 0 Debug Mode
USART_INT.DBGCTRLUSART_INT Debug Control
Address 0x42000C30
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 DBGSTOP 1 field
Field Bits What it does DBGSTOP 0 Debug Mode
I2CM.FIFOSPACEI2CM FIFO Space
Address 0x42000C34
Reset 0x0000
Access read only
Size 16-bit 2 fields
Field Bits What it does RXSPACE 12:8 Rx FIFO Filled Space TXSPACE 4:0 Tx FIFO Empty Space
I2CS.FIFOSPACEI2CS FIFO Space
Address 0x42000C34
Reset 0x0000
Access read only
Size 16-bit 2 fields
Field Bits What it does RXSPACE 12:8 Rx FIFO Filled Space TXSPACE 4:0 Tx FIFO Empty Space
SPIM.FIFOSPACESPIM FIFO Space
Address 0x42000C34
Reset 0x0000
Access read only
Size 16-bit 2 fields
Field Bits What it does RXSPACE 12:8 Rx FIFO Filled Space TXSPACE 4:0 Tx FIFO Empty Space
SPIS.FIFOSPACESPIS FIFO Space
Address 0x42000C34
Reset 0x0000
Access read only
Size 16-bit 2 fields
Field Bits What it does RXSPACE 12:8 Rx FIFO Filled Space TXSPACE 4:0 Tx FIFO Empty Space
USART_EXT.FIFOSPACEUSART_EXT FIFO Space
Address 0x42000C34
Reset 0x0000
Access read only
Size 16-bit 2 fields
Field Bits What it does RXSPACE 12:8 Rx FIFO Filled Space TXSPACE 4:0 Tx FIFO Empty Space
USART_INT.FIFOSPACEUSART_INT FIFO Space
Address 0x42000C34
Reset 0x0000
Access read only
Size 16-bit 2 fields
Field Bits What it does RXSPACE 12:8 Rx FIFO Filled Space TXSPACE 4:0 Tx FIFO Empty Space
I2CM.FIFOPTRI2CM FIFO CPU Pointers
Address 0x42000C36
Reset 0x0000
Access read/write
Size 16-bit 2 fields
Field Bits What it does CPURDPTR 11:8 CPU FIFO Read Pointer CPUWRPTR 3:0 CPU FIFO Write Pointer
I2CS.FIFOPTRI2CS FIFO CPU Pointers
Address 0x42000C36
Reset 0x0000
Access read/write
Size 16-bit 2 fields
Field Bits What it does CPURDPTR 11:8 CPU FIFO Read Pointer CPUWRPTR 3:0 CPU FIFO Write Pointer
SPIM.FIFOPTRSPIM FIFO CPU Pointers
Address 0x42000C36
Reset 0x0000
Access read/write
Size 16-bit 2 fields
Field Bits What it does CPURDPTR 11:8 CPU FIFO Read Pointer CPUWRPTR 3:0 CPU FIFO Write Pointer
SPIS.FIFOPTRSPIS FIFO CPU Pointers
Address 0x42000C36
Reset 0x0000
Access read/write
Size 16-bit 2 fields
Field Bits What it does CPURDPTR 11:8 CPU FIFO Read Pointer CPUWRPTR 3:0 CPU FIFO Write Pointer
USART_EXT.FIFOPTRUSART_EXT FIFO CPU Pointers
Address 0x42000C36
Reset 0x0000
Access read/write
Size 16-bit 2 fields
Field Bits What it does CPURDPTR 11:8 CPU FIFO Read Pointer CPUWRPTR 3:0 CPU FIFO Write Pointer
USART_INT.FIFOPTRUSART_INT FIFO CPU Pointers
Address 0x42000C36
Reset 0x0000
Access read/write
Size 16-bit 2 fields
Field Bits What it does CPURDPTR 11:8 CPU FIFO Read Pointer CPUWRPTR 3:0 CPU FIFO Write Pointer
BETA