PIC32CM2532LS00100 I2S registers

The 11 registers of I2S (Inter-IC Sound Interface), from 0x42004C00, with their reset value and every field. The PIC32CM2532LS00100 has 2513 registers in 56 peripherals, one page each.

I2S Inter-IC Sound Interface

CTRLAControl A

Address
0x42004C00
Reset
0x00
Access
read/write
  1. 7–
  2. 6–
  3. 5RXEN
  4. 4TXEN
  5. 3CKEN1
  6. 2CKEN0
  7. 1ENABLE
  8. 0SWRST
6 fields
FieldBitsWhat it does
RXEN5Rx Serializer Enable
TXEN4Tx Serializer Enable
CKEN13Clock Unit 1 Enable
CKEN02Clock Unit 0 Enable
ENABLE1Enable
SWRST0Software Reset

CLKCTRL0Clock Unit n Control

Address
0x42004C04
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
MCKOUTDIV29:24Master Clock Output Division Factor
MCKDIV21:16Master Clock Division Factor
MCKOUTINV15Master Clock Output Invert
MCKEN14Master Clock Enable
MCKSEL13Master Clock Select
  • 0 GCLK_I2S_n is used as Master Clock n source
  • 1 MCKn input pin is used as Master Clock n source
SCKOUTINV12Serial Clock Output Invert
SCKSEL11Serial Clock Select
  • 0 Divided Master Clock n is used as Serial Clock n source
  • 1 SCKn input pin is used as Serial Clock n source
FSOUTINV10Frame Sync Output Invert
FSINV9Frame Sync Invert
FSSEL8Frame Sync Select
  • 0 Divided Serial Clock n is used as Frame Sync n source
  • 1 FSn input pin is used as Frame Sync n source
BITDELAY7Data Delay from Frame Sync
  • 0 Left Justified (0 Bit Delay)
  • 1 I2S (1 Bit Delay)
FSWIDTH6:5Frame Sync Width
  • 0 Frame Sync Pulse is 1 Slot wide (default for I2S protocol)
  • 1 Frame Sync Pulse is half a Frame wide
  • 2 Frame Sync Pulse is 1 Bit wide
  • 3 Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested
NBSLOTS4:2Number of Slots in Frame
SLOTSIZE1:0Slot Size
  • 0 8-bit Slot for Clock Unit n
  • 1 16-bit Slot for Clock Unit n
  • 2 24-bit Slot for Clock Unit n
  • 3 32-bit Slot for Clock Unit n

CLKCTRL1Clock Unit n Control

Address
0x42004C08
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
MCKOUTDIV29:24Master Clock Output Division Factor
MCKDIV21:16Master Clock Division Factor
MCKOUTINV15Master Clock Output Invert
MCKEN14Master Clock Enable
MCKSEL13Master Clock Select
  • 0 GCLK_I2S_n is used as Master Clock n source
  • 1 MCKn input pin is used as Master Clock n source
SCKOUTINV12Serial Clock Output Invert
SCKSEL11Serial Clock Select
  • 0 Divided Master Clock n is used as Serial Clock n source
  • 1 SCKn input pin is used as Serial Clock n source
FSOUTINV10Frame Sync Output Invert
FSINV9Frame Sync Invert
FSSEL8Frame Sync Select
  • 0 Divided Serial Clock n is used as Frame Sync n source
  • 1 FSn input pin is used as Frame Sync n source
BITDELAY7Data Delay from Frame Sync
  • 0 Left Justified (0 Bit Delay)
  • 1 I2S (1 Bit Delay)
FSWIDTH6:5Frame Sync Width
  • 0 Frame Sync Pulse is 1 Slot wide (default for I2S protocol)
  • 1 Frame Sync Pulse is half a Frame wide
  • 2 Frame Sync Pulse is 1 Bit wide
  • 3 Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested
NBSLOTS4:2Number of Slots in Frame
SLOTSIZE1:0Slot Size
  • 0 8-bit Slot for Clock Unit n
  • 1 16-bit Slot for Clock Unit n
  • 2 24-bit Slot for Clock Unit n
  • 3 32-bit Slot for Clock Unit n

INTENCLRInterrupt Enable Clear

Address
0x42004C0C
Reset
0x0000
Access
read/write
Size
16-bit
8 fields
FieldBitsWhat it does
TXUR113Transmit Underrun 1 Interrupt Enable
TXUR012Transmit Underrun 0 Interrupt Enable
TXRDY19Transmit Ready 1 Interrupt Enable
TXRDY08Transmit Ready 0 Interrupt Enable
RXOR15Receive Overrun 1 Interrupt Enable
RXOR04Receive Overrun 0 Interrupt Enable
RXRDY11Receive Ready 1 Interrupt Enable
RXRDY00Receive Ready 0 Interrupt Enable

INTENSETInterrupt Enable Set

Address
0x42004C10
Reset
0x0000
Access
read/write
Size
16-bit
8 fields
FieldBitsWhat it does
TXUR113Transmit Underrun 1 Interrupt Enable
TXUR012Transmit Underrun 0 Interrupt Enable
TXRDY19Transmit Ready 1 Interrupt Enable
TXRDY08Transmit Ready 0 Interrupt Enable
RXOR15Receive Overrun 1 Interrupt Enable
RXOR04Receive Overrun 0 Interrupt Enable
RXRDY11Receive Ready 1 Interrupt Enable
RXRDY00Receive Ready 0 Interrupt Enable

INTFLAGInterrupt Flag Status and Clear

Address
0x42004C14
Reset
0x0000
Access
read/write
Size
16-bit
8 fields
FieldBitsWhat it does
TXUR113Transmit Underrun 1
TXUR012Transmit Underrun 0
TXRDY19Transmit Ready 1
TXRDY08Transmit Ready 0
RXOR15Receive Overrun 1
RXOR04Receive Overrun 0
RXRDY11Receive Ready 1
RXRDY00Receive Ready 0

SYNCBUSYSynchronization Status

Address
0x42004C18
Reset
0x0000
Access
read only
Size
16-bit
8 fields
FieldBitsWhat it does
RXDATA9Rx Data Synchronization Status
TXDATA8Tx Data Synchronization Status
RXEN5Rx Serializer Enable Synchronization Status
TXEN4Tx Serializer Enable Synchronization Status
CKEN13Clock Unit 1 Enable Synchronization Status
CKEN02Clock Unit 0 Enable Synchronization Status
ENABLE1Enable Synchronization Status
SWRST0Software Reset Synchronization Status

TXCTRLTx Serializer Control

Address
0x42004C20
Reset
0x00000000
Access
read/write
Size
32-bit
17 fields
FieldBitsWhat it does
DMA25Single or Multiple DMA Channels
  • 0 Single DMA channel
  • 1 One DMA channel per data channel
MONO24Mono Mode
  • 0 Normal mode
  • 1 Left channel data is duplicated to right channel
SLOTDIS723Slot 7 Disabled for this Serializer
SLOTDIS622Slot 6 Disabled for this Serializer
SLOTDIS521Slot 5 Disabled for this Serializer
SLOTDIS420Slot 4 Disabled for this Serializer
SLOTDIS319Slot 3 Disabled for this Serializer
SLOTDIS218Slot 2 Disabled for this Serializer
SLOTDIS117Slot 1 Disabled for this Serializer
SLOTDIS016Slot 0 Disabled for this Serializer
BITREV15Data Formatting Bit Reverse
  • 0 Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)
  • 1 Transfer Data Least Significant Bit (LSB) first
EXTEND14:13Data Formatting Bit Extension
  • 0 Extend with zeroes
  • 1 Extend with ones
  • 2 Extend with Most Significant Bit
  • 3 Extend with Least Significant Bit
WORDADJ12Data Word Formatting Adjust
  • 0 Data is right adjusted in word
  • 1 Data is left adjusted in word
DATASIZE10:8Data Word Size
  • 0 32 bits
  • 1 24 bits
  • 2 20 bits
  • 3 18 bits
  • 4 16 bits
  • 5 16 bits compact stereo
  • 6 8 bits
  • 7 8 bits compact stereo
SLOTADJ7Data Slot Formatting Adjust
  • 0 Data is right adjusted in slot
  • 1 Data is left adjusted in slot
TXSAME4Transmit Data when Underrun
  • 0 Zero data transmitted in case of underrun
  • 1 Last data transmitted in case of underrun
TXDEFAULT3:2Line Default Line when Slot Disabled
  • 0 Output Default Value is 0
  • 1 Output Default Value is 1
  • 3 Output Default Value is high impedance

RXCTRLRx Serializer Control

Address
0x42004C24
Reset
0x00000000
Access
read/write
Size
32-bit
18 fields
FieldBitsWhat it does
RXLOOP26Loop-back Test Mode
DMA25Single or Multiple DMA Channels
  • 0 Single DMA channel
  • 1 One DMA channel per data channel
MONO24Mono Mode
  • 0 Normal mode
  • 1 Left channel data is duplicated to right channel
SLOTDIS723Slot 7 Disabled for this Serializer
SLOTDIS622Slot 6 Disabled for this Serializer
SLOTDIS521Slot 5 Disabled for this Serializer
SLOTDIS420Slot 4 Disabled for this Serializer
SLOTDIS319Slot 3 Disabled for this Serializer
SLOTDIS218Slot 2 Disabled for this Serializer
SLOTDIS117Slot 1 Disabled for this Serializer
SLOTDIS016Slot 0 Disabled for this Serializer
BITREV15Data Formatting Bit Reverse
  • 0 Transfer Data Most Significant Bit (MSB) first (default for I2S protocol)
  • 1 Transfer Data Least Significant Bit (LSB) first
EXTEND14:13Data Formatting Bit Extension
  • 0 Extend with zeroes
  • 1 Extend with ones
  • 2 Extend with Most Significant Bit
  • 3 Extend with Least Significant Bit
WORDADJ12Data Word Formatting Adjust
  • 0 Data is right adjusted in word
  • 1 Data is left adjusted in word
DATASIZE10:8Data Word Size
  • 0 32 bits
  • 1 24 bits
  • 2 20 bits
  • 3 18 bits
  • 4 16 bits
  • 5 16 bits compact stereo
  • 6 8 bits
  • 7 8 bits compact stereo
SLOTADJ7Data Slot Formatting Adjust
  • 0 Data is right adjusted in slot
  • 1 Data is left adjusted in slot
CLKSEL5Clock Unit Selection
  • 0 Use Clock Unit 0
  • 1 Use Clock Unit 1
SERMODE1:0Serializer Mode
  • 0 Receive
  • 2 Receive one PDM data on each serial clock edge

TXDATATx Data

Address
0x42004C30
Reset
0x00000000
Access
write only
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0Sample Data

RXDATARx Data

Address
0x42004C34
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
DATA31:0Sample Data