PIC32CM3204GV00048 SERCOM4 registers The 56 registers of SERCOM4 (Serial Communication Interface), from 0x42001800, with their reset value and every field. The PIC32CM3204GV00048 has 779 registers in 31 peripherals, one page each.
SERCOM4 Serial Communication Interface I2CM.CTRLAI2CM Control A
Address 0x42001800
Reset 0x00000000
Access read/write
Size 32-bit 8 fields
Field Bits What it does LOWTOUT 30 SCL Low Time-out INACTOUT 29:28 Inactive Time-out0 Disabled1 5-6 SCL Time-Out(50-60us)2 10-11 SCL Time-Out(100-110us)3 20-21 SCL Time-Out(200-210us) SDAHOLD 21:20 SDA Hold Time0 Disabled1 50-100ns hold time2 300-600ns hold time3 400-800ns hold time PINOUT 16 Pin Usage RUNSTDBY 7 Run in Standby MODE 4:2 Operating Mode0 USART with external clock1 USART with internal clock2 SPI in slave operation3 SPI in master operation4 I2C slave operation5 I2C master operation ENABLE 1 Enable SWRST 0 Software Reset
I2CS.CTRLAI2CS Control A
Address 0x42001800
Reset 0x00000000
Access read/write
Size 32-bit 7 fields
Field Bits What it does LOWTOUT 30 SCL Low Time-out SDAHOLD 21:20 SDA Hold Time0 Disabled1 50-100ns hold time2 300-600ns hold time3 400-800ns hold time PINOUT 16 Pin Usage RUNSTDBY 7 Run in Standby MODE 4:2 Operating Mode0 USART with external clock1 USART with internal clock2 SPI in slave operation3 SPI in master operation4 I2C slave operation5 I2C master operation ENABLE 1 Enable SWRST 0 Software Reset
SPIM.CTRLASPIM Control A
Address 0x42001800
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does DORD 30 Data Order0 MSB is transferred first1 LSB is transferred first CPOL 29 Clock Polarity0 SCK is low when idle1 SCK is high when idle CPHA 28 Clock Phase0 The data is sampled on a leading SCK edge and changed on a trailing SCK edge1 The data is sampled on a trailing SCK edge and changed on a leading SCK edge FORM 27:24 Frame Format0 SPI Frame2 SPI Frame with Addr DIPO 21:20 Data In Pinout0 SERCOM PAD[0]1 SERCOM PAD[1]2 SERCOM PAD[2]3 SERCOM PAD[3] DOPO 17:16 Data Out Pinout0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2]1 DO on PAD[2], SCK on PAD[3] and SS on PAD[1]2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2]3 DO on PAD[0], SCK on PAD[3] and SS on PAD[1] IBON 8 Immediate Buffer Overflow Notification RUNSTDBY 7 Run In Standby MODE 4:2 Operating Mode0 USART with external clock1 USART with internal clock2 SPI in slave operation3 SPI in master operation4 I2C slave operation5 I2C master operation ENABLE 1 Enable SWRST 0 Software Reset
SPIS.CTRLASPIS Control A
Address 0x42001800
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does DORD 30 Data Order0 MSB is transferred first1 LSB is transferred first CPOL 29 Clock Polarity0 SCK is low when idle1 SCK is high when idle CPHA 28 Clock Phase0 The data is sampled on a leading SCK edge and changed on a trailing SCK edge1 The data is sampled on a trailing SCK edge and changed on a leading SCK edge FORM 27:24 Frame Format0 SPI Frame2 SPI Frame with Addr DIPO 21:20 Data In Pinout0 SERCOM PAD[0]1 SERCOM PAD[1]2 SERCOM PAD[2]3 SERCOM PAD[3] DOPO 17:16 Data Out Pinout0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2]1 DO on PAD[2], SCK on PAD[3] and SS on PAD[1]2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2]3 DO on PAD[0], SCK on PAD[3] and SS on PAD[1] IBON 8 Immediate Buffer Overflow Notification RUNSTDBY 7 Run In Standby MODE 4:2 Operating Mode0 USART with external clock1 USART with internal clock2 SPI in slave operation3 SPI in master operation4 I2C slave operation5 I2C master operation ENABLE 1 Enable SWRST 0 Software Reset
USART_EXT.CTRLAUSART_EXT Control A
Address 0x42001800
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does DORD 30 Data Order0 MSB is transmitted first1 LSB is transmitted first CPOL 29 Clock Polarity0 TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge1 TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge CMODE 28 Communication Mode0 Asynchronous Communication1 Synchronous Communication FORM 27:24 Frame Format0 USART frame1 USART frame with parity RXPO 21:20 Receive Data Pinout0 SERCOM PAD[0] is used for data reception1 SERCOM PAD[1] is used for data reception2 SERCOM PAD[2] is used for data reception3 SERCOM PAD[3] is used for data reception TXPO 16 Transmit Data Pinout0 PAD[0] = TxD; PAD[1] = XCK1 PAD[2] = TxD; PAD[3] = XCK IBON 8 Immediate Buffer Overflow Notification RUNSTDBY 7 Run In Standby MODE 4:2 Operating Mode0 USART with external clock1 USART with internal clock2 SPI in slave operation3 SPI in master operation4 I2C slave operation5 I2C master operation ENABLE 1 Enable SWRST 0 Software Reset
USART_INT.CTRLAUSART_INT Control A
Address 0x42001800
Reset 0x00000000
Access read/write
Size 32-bit 11 fields
Field Bits What it does DORD 30 Data Order0 MSB is transmitted first1 LSB is transmitted first CPOL 29 Clock Polarity0 TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge1 TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge CMODE 28 Communication Mode0 Asynchronous Communication1 Synchronous Communication FORM 27:24 Frame Format0 USART frame1 USART frame with parity RXPO 21:20 Receive Data Pinout0 SERCOM PAD[0] is used for data reception1 SERCOM PAD[1] is used for data reception2 SERCOM PAD[2] is used for data reception3 SERCOM PAD[3] is used for data reception TXPO 16 Transmit Data Pinout0 PAD[0] = TxD; PAD[1] = XCK1 PAD[2] = TxD; PAD[3] = XCK IBON 8 Immediate Buffer Overflow Notification RUNSTDBY 7 Run In Standby MODE 4:2 Operating Mode0 USART with external clock1 USART with internal clock2 SPI in slave operation3 SPI in master operation4 I2C slave operation5 I2C master operation ENABLE 1 Enable SWRST 0 Software Reset
I2CM.CTRLBI2CM Control B
Address 0x42001804
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does ACKACT 18 Acknowledge Action CMD 17:16 Command QCEN 9 Quick Command Enable SMEN 8 Smart Mode Enable
I2CS.CTRLBI2CS Control B
Address 0x42001804
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does ACKACT 18 Acknowledge Action CMD 17:16 Command AMODE 15:14 Address Mode SMEN 8 Smart Mode Enable
SPIM.CTRLBSPIM Control B
Address 0x42001804
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RXEN 17 Receiver Enable AMODE 15:14 Address Mode0 ADDRMASK is used as a mask to the ADDR register.1 The slave responds to the 2 unique addresses in ADDR and ADDRMASK.2 The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit. PLOADEN 6 Slave Data Preload Enable CHSIZE 2:0 Character Size
SPIS.CTRLBSPIS Control B
Address 0x42001804
Reset 0x00000000
Access read/write
Size 32-bit 4 fields
Field Bits What it does RXEN 17 Receiver Enable AMODE 15:14 Address Mode0 ADDRMASK is used as a mask to the ADDR register.1 The slave responds to the 2 unique addresses in ADDR and ADDRMASK.2 The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit. PLOADEN 6 Slave Data Preload Enable CHSIZE 2:0 Character Size
USART_EXT.CTRLBUSART_EXT Control B
Address 0x42001804
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does RXEN 17 Receiver Enable TXEN 16 Transmitter Enable PMODE 13 Parity Mode0 Even Parity1 Odd Parity SFDE 9 Start of Frame Detection Enable SBMODE 6 Stop Bit Mode0 One Stop Bit1 Two Stop Bits CHSIZE 2:0 Character Size0 8 Bits1 9 Bits5 5 Bits6 6 Bits7 7 Bits
USART_INT.CTRLBUSART_INT Control B
Address 0x42001804
Reset 0x00000000
Access read/write
Size 32-bit 6 fields
Field Bits What it does RXEN 17 Receiver Enable TXEN 16 Transmitter Enable PMODE 13 Parity Mode0 Even Parity1 Odd Parity SFDE 9 Start of Frame Detection Enable SBMODE 6 Stop Bit Mode0 One Stop Bit1 Two Stop Bits CHSIZE 2:0 Character Size0 8 Bits1 9 Bits5 5 Bits6 6 Bits7 7 Bits
I2CM.DBGCTRLI2CM Debug Control
Address 0x42001808
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 DBGSTOP 1 field
Field Bits What it does DBGSTOP 0 Debug Stop Mode
SPIM.DBGCTRLSPIM Debug Control
Address 0x42001808
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 DBGSTOP 1 field
Field Bits What it does DBGSTOP 0 Debug Stop Mode
SPIS.DBGCTRLSPIS Debug Control
Address 0x42001808
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 DBGSTOP 1 field
Field Bits What it does DBGSTOP 0 Debug Stop Mode
USART_EXT.DBGCTRLUSART_EXT Debug Control
Address 0x42001808
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 DBGSTOP 1 field
Field Bits What it does DBGSTOP 0 Debug Stop Mode
USART_INT.DBGCTRLUSART_INT Debug Control
Address 0x42001808
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 DBGSTOP 1 field
Field Bits What it does DBGSTOP 0 Debug Stop Mode
I2CM.BAUDI2CM Baud Rate
Address 0x4200180A
Reset 0x0000
Access read/write
Size 16-bit 2 fields
Field Bits What it does BAUDLOW 15:8 Master Baud Rate Low BAUD 7:0 Master Baud Rate
SPIM.BAUDSPIM Baud Rate
Address 0x4200180A
Reset 0x00
Access read/write 7 BAUD7 6 BAUD6 5 BAUD5 4 BAUD4 3 BAUD3 2 BAUD2 1 BAUD1 0 BAUD0 1 field
Field Bits What it does BAUD 7:0 Baud Register
SPIS.BAUDSPIS Baud Rate
Address 0x4200180A
Reset 0x00
Access read/write 7 BAUD7 6 BAUD6 5 BAUD5 4 BAUD4 3 BAUD3 2 BAUD2 1 BAUD1 0 BAUD0 1 field
Field Bits What it does BAUD 7:0 Baud Register
USART_EXT.BAUDUSART_EXT Baud
Address 0x4200180A
Reset 0x0000
Access read/write
Size 16-bit 1 field
Field Bits What it does BAUD 15:0 Baud Value
USART_INT.BAUDUSART_INT Baud
Address 0x4200180A
Reset 0x0000
Access read/write
Size 16-bit 1 field
Field Bits What it does BAUD 15:0 Baud Value
I2CM.INTENCLRI2CM Interrupt Enable Clear
Address 0x4200180C
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 SB 0 MB 2 fields
Field Bits What it does SB 1 Slave on Bus Interrupt Enable MB 0 Master on Bus Interrupt Enable
I2CS.INTENCLRI2CS Interrupt Enable Clear
Address 0x4200180C
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 DRDY 1 AMATCH 0 PREC 3 fields
Field Bits What it does DRDY 2 Data Ready Interrupt Enable AMATCH 1 Address Match Interrupt Enable PREC 0 Stop Received Interrupt Enable
SPIM.INTENCLRSPIM Interrupt Enable Clear
Address 0x4200180C
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 RXC 1 TXC 0 DRE 3 fields
Field Bits What it does RXC 2 Receive Complete Interrupt Enable TXC 1 Transmit Complete Interrupt Enable DRE 0 Data Register Empty Interrupt Enable
SPIS.INTENCLRSPIS Interrupt Enable Clear
Address 0x4200180C
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 RXC 1 TXC 0 DRE 3 fields
Field Bits What it does RXC 2 Receive Complete Interrupt Enable TXC 1 Transmit Complete Interrupt Enable DRE 0 Data Register Empty Interrupt Enable
USART_EXT.INTENCLRUSART_EXT Interrupt Enable Clear
Address 0x4200180C
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 RXS 2 RXC 1 TXC 0 DRE 4 fields
Field Bits What it does RXS 3 Receive Start Interrupt Disable RXC 2 Receive Complete Interrupt Enable TXC 1 Transmit Complete Interrupt Enable DRE 0 Data Register Empty Interrupt Enable
USART_INT.INTENCLRUSART_INT Interrupt Enable Clear
Address 0x4200180C
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 RXS 2 RXC 1 TXC 0 DRE 4 fields
Field Bits What it does RXS 3 Receive Start Interrupt Disable RXC 2 Receive Complete Interrupt Enable TXC 1 Transmit Complete Interrupt Enable DRE 0 Data Register Empty Interrupt Enable
I2CM.INTENSETI2CM Interrupt Enable Set
Address 0x4200180D
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 SB 0 MB 2 fields
Field Bits What it does SB 1 Slave on Bus Interrupt Enable MB 0 Master on Bus Interrupt Enable
I2CS.INTENSETI2CS Interrupt Enable Set
Address 0x4200180D
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 DRDY 1 AMATCH 0 PREC 3 fields
Field Bits What it does DRDY 2 Data Ready Interrupt Enable AMATCH 1 Address Match Interrupt Enable PREC 0 Stop Received Interrupt Enable
SPIM.INTENSETSPIM Interrupt Enable Set
Address 0x4200180D
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 RXC 1 TXC 0 DRE 3 fields
Field Bits What it does RXC 2 Receive Complete Interrupt Enable TXC 1 Transmit Complete Interrupt Enable DRE 0 Data Register Empty Interrupt Enable
SPIS.INTENSETSPIS Interrupt Enable Set
Address 0x4200180D
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 RXC 1 TXC 0 DRE 3 fields
Field Bits What it does RXC 2 Receive Complete Interrupt Enable TXC 1 Transmit Complete Interrupt Enable DRE 0 Data Register Empty Interrupt Enable
USART_EXT.INTENSETUSART_EXT Interrupt Enable Set
Address 0x4200180D
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 RXS 2 RXC 1 TXC 0 DRE 4 fields
Field Bits What it does RXS 3 Receive Start Interrupt Enable RXC 2 Receive Complete Interrupt Enable TXC 1 Transmit Complete Interrupt Enable DRE 0 Data Register Empty Interrupt Enable
USART_INT.INTENSETUSART_INT Interrupt Enable Set
Address 0x4200180D
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 RXS 2 RXC 1 TXC 0 DRE 4 fields
Field Bits What it does RXS 3 Receive Start Interrupt Enable RXC 2 Receive Complete Interrupt Enable TXC 1 Transmit Complete Interrupt Enable DRE 0 Data Register Empty Interrupt Enable
I2CM.INTFLAGI2CM Interrupt Flag Status and Clear
Address 0x4200180E
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 SB 0 MB 2 fields
Field Bits What it does SB 1 Slave on Bus MB 0 Master on Bus
I2CS.INTFLAGI2CS Interrupt Flag Status and Clear
Address 0x4200180E
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 DRDY 1 AMATCH 0 PREC 3 fields
Field Bits What it does DRDY 2 Data Ready AMATCH 1 Address Match PREC 0 Stop Received
SPIM.INTFLAGSPIM Interrupt Flag Status and Clear
Address 0x4200180E
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 RXC 1 TXC 0 DRE 3 fields
Field Bits What it does RXC 2 Receive Complete TXC 1 Transmit Complete DRE 0 Data Register Empty
SPIS.INTFLAGSPIS Interrupt Flag Status and Clear
Address 0x4200180E
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 RXC 1 TXC 0 DRE 3 fields
Field Bits What it does RXC 2 Receive Complete TXC 1 Transmit Complete DRE 0 Data Register Empty
USART_EXT.INTFLAGUSART_EXT Interrupt Flag Status and Clear
Address 0x4200180E
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 RXS 2 RXC 1 TXC 0 DRE 4 fields
Field Bits What it does RXS 3 Receive Start Interrupt RXC 2 Receive Complete TXC 1 Transmit Complete DRE 0 Data Register Empty
USART_INT.INTFLAGUSART_INT Interrupt Flag Status and Clear
Address 0x4200180E
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 RXS 2 RXC 1 TXC 0 DRE 4 fields
Field Bits What it does RXS 3 Receive Start Interrupt RXC 2 Receive Complete TXC 1 Transmit Complete DRE 0 Data Register Empty
I2CM.STATUSI2CM Status
Address 0x42001810
Reset 0x0000
Access read/write
Size 16-bit 7 fields
Field Bits What it does SYNCBUSY 15 Synchronization Busy CLKHOLD 7 Clock Hold LOWTOUT 6 SCL Low Time-out BUSSTATE 5:4 Bus State RXNACK 2 Received Not Acknowledge ARBLOST 1 Arbitration Lost BUSERR 0 Bus Error
I2CS.STATUSI2CS Status
Address 0x42001810
Reset 0x0000
Access read/write
Size 16-bit 8 fields
Field Bits What it does SYNCBUSY 15 Synchronization Busy CLKHOLD 7 Clock Hold LOWTOUT 6 SCL Low Time-out SR 4 Repeated Start DIR 3 Read / Write Direction RXNACK 2 Received Not Acknowledge COLL 1 Transmit Collision BUSERR 0 Bus Error
SPIM.STATUSSPIM Status
Address 0x42001810
Reset 0x0000
Access read/write
Size 16-bit 2 fields
Field Bits What it does SYNCBUSY 15 Synchronization Busy BUFOVF 2 Buffer Overflow
SPIS.STATUSSPIS Status
Address 0x42001810
Reset 0x0000
Access read/write
Size 16-bit 2 fields
Field Bits What it does SYNCBUSY 15 Synchronization Busy BUFOVF 2 Buffer Overflow
USART_EXT.STATUSUSART_EXT Status
Address 0x42001810
Reset 0x0000
Access read/write
Size 16-bit 4 fields
Field Bits What it does SYNCBUSY 15 Synchronization Busy BUFOVF 2 Buffer Overflow FERR 1 Frame Error PERR 0 Parity Error
USART_INT.STATUSUSART_INT Status
Address 0x42001810
Reset 0x0000
Access read/write
Size 16-bit 4 fields
Field Bits What it does SYNCBUSY 15 Synchronization Busy BUFOVF 2 Buffer Overflow FERR 1 Frame Error PERR 0 Parity Error
I2CM.ADDRI2CM Address
Address 0x42001814
Reset 0x00
Access read/write 7 ADDR7 6 ADDR6 5 ADDR5 4 ADDR4 3 ADDR3 2 ADDR2 1 ADDR1 0 ADDR0 1 field
Field Bits What it does ADDR 7:0 Address
I2CS.ADDRI2CS Address
Address 0x42001814
Reset 0x00000000
Access read/write
Size 32-bit 3 fields
Field Bits What it does ADDRMASK 23:17 Address Mask ADDR 7:1 Address GENCEN 0 General Call Address Enable
SPIM.ADDRSPIM Address
Address 0x42001814
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does ADDRMASK 23:16 Address Mask ADDR 7:0 Address
SPIS.ADDRSPIS Address
Address 0x42001814
Reset 0x00000000
Access read/write
Size 32-bit 2 fields
Field Bits What it does ADDRMASK 23:16 Address Mask ADDR 7:0 Address
I2CM.DATAI2CM Data
Address 0x42001818
Reset 0x00
Access read/write 7 DATA7 6 DATA6 5 DATA5 4 DATA4 3 DATA3 2 DATA2 1 DATA1 0 DATA0 1 field
Field Bits What it does DATA 7:0 Data
I2CS.DATAI2CS Data
Address 0x42001818
Reset 0x00
Access read/write 7 DATA7 6 DATA6 5 DATA5 4 DATA4 3 DATA3 2 DATA2 1 DATA1 0 DATA0 1 field
Field Bits What it does DATA 7:0 Data
SPIM.DATASPIM Data
Address 0x42001818
Reset 0x0000
Access read/write
Size 16-bit 1 field
Field Bits What it does DATA 8:0 Data
SPIS.DATASPIS Data
Address 0x42001818
Reset 0x0000
Access read/write
Size 16-bit 1 field
Field Bits What it does DATA 8:0 Data Value
USART_EXT.DATAUSART_EXT Data
Address 0x42001818
Reset 0x0000
Access read/write
Size 16-bit 1 field
Field Bits What it does DATA 8:0 Data
USART_INT.DATAUSART_INT Data
Address 0x42001818
Reset 0x0000
Access read/write
Size 16-bit 1 field
Field Bits What it does DATA 8:0 Data
BETA