PIC32CM5112GC00100 FCR registers

The 27 registers of FCR (Polaris Flash Read Controller), from 0x44002000, with their reset value and every field. The PIC32CM5112GC00100 has 2253 registers in 57 peripherals, one page each.

FCR Polaris Flash Read Controller

CTRLACTRL A REGISTER

Address
0x44002000
Reset
0x00008000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
RDBUFWS16Read Buffer Wait StatesPer AHB port control of deterministic or zero wait state read buffer access.
  • 0 0 Wait States
  • 1 ADRWS + FWS wait state for hits to AHB read buffer
AUTOWS15Automatic Wait State Enable.
  • 0 Use FWS: Total flash wait states are ADRWS + FWS
  • 1 Use Automatic wait states: Total flash wait states are ADRWS + Taws
ADRWS14Address Wait State Enable
  • 0 Add 0 Address Wait States - allowing for higher performance at lower clock frequencies
  • 1 Add 1 Address Wait State - allowing for higher clock frequencies
FWS11:8Flash Access Time Defined in terms of AHB Clock Wait States
  • 0 Zero Wait States
  • 1 One Wait State
  • 14 Fourteen Wait States
  • 15 Fifteen Wait States
PRIV2Privileged Access Only
  • 0 Macro register accessible in privileged and unprivileged accesses.
  • 1 Macro registers only accessible in privileged accesses

CTRLBCTRL B REGISTER

Address
0x44002004
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
PREFDIS17Prefetch Disable
  • 0 Predictive Prefetch Enabled
  • 1 Predictive Prefetch Disabled
CHEDIS16Cache Disable
  • 0 Cache Enabled; Accesses to flash use AUTOWS/FSW selection.
  • 1 Cache Disabled; Interface uses RDBUFWS selection.
SLP9:8NVM Power Reduction Mode selection during System Standby Sleep
  • 0 Maintain state of STATUS.PRM on entry to Standby
  • 1 RSVD
  • 2 Enter Flash Hibernate on entry to Standby w/ wakeup to Auto Standby
  • 3 Enter Flash Hibernate on entry to Standby w/ wakeup on first access
CHEINV7Cache InvalidateCache invalidation takes 1 clock cycle, but may be delayed by an active read.
  • 0 No Action
  • 1 Invalidate Cache
PRM0Set NVM Power Reduction Mode
  • 0 No Action
  • 1 Toggle the Flash Power Mode

INTENCLRInterrupt Enable Clear REGISTER

Address
0x44002008
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
FLTCAP16ECC Fault Capture Clear Enable
  • 0 Interrupt Disabled
  • 1 Interrupt Enabled
CRCERR9CRC Error Clear Enable
  • 0 Interrupt Disabled
  • 1 Interrupt Enabled
CRCDONE8CRC Calculation Done Clear Enable
  • 0 Interrupt Disabled
  • 1 Interrupt Enabled
SERR0Flash SEC Interrupt Clear Enable
  • 0 Interrupt Disabled
  • 1 Interrupt Enabled

INTENSETInterrupt Enable SET REGISTER

Address
0x4400200C
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
FLTCAP16ECC Fault Capture Set Enable
  • 0 Interrupt Disabled
  • 1 Interrupt Enabled
CRCERR9CRC Error Set Enable
  • 0 Interrupt Disabled
  • 1 Interrupt Enabled
CRCDONE8CRC Calculation Done Set Enable
  • 0 Interrupt Disabled
  • 1 Interrupt Enabled
SERR0Flash SEC Interrupt Set Enable
  • 0 Interrupt Disabled
  • 1 Interrupt Enabled

INTFLAGInterrupt Flag REGISTER

Address
0x44002010
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
FLTCAP16ECC Fault Capture Flag
  • 0 No Interrupt Pending
  • 1 An ECC Fault Capture, related to FLTMD[], occurred
CRCERR9CRC Error Flag
  • 0 No Interrupt Pending
  • 1 CRCACC Is Not Equal to the XOR of CRCSUM and CRCFXOR
CRCDONE8CRC Calculation Done Flag
  • 0 No Interrupt Pending
  • 1 Calculation Done
SERR0Flash SEC Interrupt Flag
  • 0 No Interrupt Pending
  • 1 SECCNT Count reached

INTFLAGSETInterrupt Flag Set REGISTER

Address
0x44002014
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
FLTCAP16ECC Fault Capture Flag
  • 0 No effect
  • 1 Set Interrupt Pending
CRCERR9CRC Error Flag
  • 0 No effect
  • 1 Set Interrupt Pending
CRCDONE8CRC Calculation Done Flag
  • 0 No effect
  • 1 Set Interrupt Pending
SERR0Flash SEC Interrupt Flag
  • 0 No Interrupt Pending
  • 1 SECCNT Count reached

STATUSStatus REGISTER

Address
0x44002018
Reset
0xE0000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
PRM0NVM Power Reduction Mode Status
  • 0 Flash is Ready (for read or NVMOP)
  • 1 Flash is Powered Down and wakes on first access (read or NVMOP)

DBGCTRLDebug Control CTRL REGISTER

Address
0x4400201C
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
DBGECC2:1Debug ECC ModeECC errors from debugger reads are:
  • 0 Corrected per ECCCTRL; No Bus ERR; INTFLAG, SEC counter, and FLT logic are not updated.
  • 1 Not corrected; No Bus Error; INTFLAG, SEC counter, and FLT logic are not updated.
  • 2 Corrected per ECCCTRL; Bus Error, INTFLAG, SEC counter, and FLT logic operates as setup.
  • 3 Don't use but same as 01 (DISABLE)
CRCRUN0CRC Debug Run Enable
  • 0 CRC Logic Halts in Debug Mode
  • 1 CRC Logic Runs in Debug Mode.

ECCCTRLECC Control REGISTER

Address
0x44002020
Reset
0x00000040
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
SECCNT15:8Flash SEC Count
ECCUNLCK6NVM ECC Mode Control Unlock
  • 0 ECCUNLCK and ECCCTL[1:0] cannot be written
  • 1 ECCUNLCK and ECCCTL[1:0] can be written
ECCCTL5:4NVM ECC Mode Control - restricts one or more NVMOPs
  • 0 ECC Writes with ECC Reads (NVMOP = Single Program Operation disabled)
  • 1 Dynamic Writes with Dynamic Reads
  • 2 ECC Writes with Dynamic Reads (NVMOP = Single Program Operation disabled)
  • 3 Dynamic Writes with No Error Check Reads

CRCCTRLCRC Control REGISTER

Address
0x44002024
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
RUNSTDBY5CRC Run in Standby
  • 0 CRC Halts in Standby
  • 1 CRC Runs in Standby but only if STATUS.PRM=0 (i.e. Flash is in Auto Standby)
CRCEN1Start CRC Calculation
  • 0 Stops CRC calculation.
  • 1 CRC Calculation Enabled (w/ start on write to 1).
CRCRST0CRC Reset
  • 0 No Action
  • 1 Resets all CRC SFR bits.

CRCMODECRC MODE REGISTER

Address
0x44002028
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
PERIOD27:16Read Period in PerCLK counts
RIN15CRC Reflected Input
  • 0 The LFSR CRC is calculated Most Significant Bit first (Not Reflected)
  • 1 The LFSR CRC is calculated Least Significant Bit first (Reflected)
ROUT14CRC Reflected Output
  • 0 The CRCACC is Not Reflected
  • 1 The CRCACC is Reflected (before the Final XOR)
AUTOR13CRC Auto Repeat
  • 0 Perform CRC calculation once then set DONE and if needed, CRCERR.
  • 1 Continually Repeat CRC calculation; stop on error, set CRCDONE and CRCERR
PLEN3212Polynomial Length Select
  • 0 Polynomial is 16-bits
  • 1 Polynomial is 32-bits

CRCPAUSECRC Pause REGISTER

Address
0x4400202C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
PAUSE0CRC Pause
  • 0 CRC Reads Flash as Required
  • 1 Pause CRC Reads of Flash

CRCMADRCRC Message Address REGISTER

Address
0x44002030
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CRCMADR27:0Message Start Address in Flash

CRCMLENCRC Message Length REGISTER

Address
0x44002034
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CRCMLEN19:0Message Length in Bytes

CRCIVCRC Initial Value REGISTER

Address
0x44002038
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CRCIV31:0CRC Initial Value

CRCACCCRC Accumulator REGISTER

Address
0x4400203C
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
CRCACC31:0CRC Accumulator Result

CRCPOLYCRC Polynomial REGISTER

Address
0x44002040
Reset
0x00000001
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CRCPOLY31:0CRC Polynomial Coefficients for LFSR
  • 0 Disable the XOR input to the shift register at the associated bit position
  • 1 Enable the XOR input to the shift register at the associated bit position

CRCFXORCRC Final XOR REGISTER

Address
0x44002044
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CRCFXOR31:0CRC Final XOR
  • 0 Disable the Final XOR at the associated bit position
  • 1 Enable the Final XOR at the associated bit position

CRCSUMCRC CheckSUM REGISTER

Address
0x44002048
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CRCSUM31:0CRC Checksum

FFLTCTRLFlash ECC Fault Control REGISTER

Address
0x4400204C
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
FLTEN1ECC Fault Enable bit
  • 0 ECC Fault Injection Disabled
  • 1 ECC Fault Injection Enabled (module performs operation selected by FFLTMODE.FLTMD)
FLTRST0Fault Reset
  • 0 No Action
  • 1 Resets all FLT SFR bits.

FFLTMODEFlash ECC Fault Mode REGISTER

Address
0x44002050
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
FLTMD14:12Fault Mode Control
  • 0 Fault Injection Disabled
  • 2 Fault Capture Mode Enabled - Captures the address (in FLTADR) and Syndrome in (FLTSYN)
  • 4 Single Fault Injection (at bit selected by FLT1PTR) for Reads
  • 5 Double Fault Injection for Reads
  • 6 Single Fault Injection (at bit selected by FLT1PTR) for Writes
  • 7 Double Fault Injection for Writes
CTLFLT10:8ECC/Parity Control Fault bits
  • 0 No Fault Injected
  • 1 Inject a Fault on to the associated ECC/Parity Control bits (CTL[n])

FFLTPTRFlash ECC Fault Pointer REGISTER

Address
0x44002054
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
FLTPTR223:16Fault 2 Injection Pointer
FLTPTR17:0Fault 1 Injection Pointer

FFLTADRFlash ECC Fault Address REGISTER

Address
0x44002058
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
FLTADR27:0Fault Injection Address

FFLTCAPFlash ECC Fault Capture Address REGISTER

Address
0x4400205C
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
FLTADR27:0Fault Capture Address

FFLTPARFlash ECC Fault Parity REGISTER

Address
0x44002060
Reset
0x00000000
Access
read only
Size
32-bit
4 fields
FieldBitsWhat it does
SECOUT23:16The Calculated Single Error Parity bits
DEDIN15The Overall Parity from Flash
SECIN7:0The Single Error Parity bits from Flash
DEDOUT31The Calculated Overall Parity used in Double Error Detection

FFLTSYNFlash ECC Fault Syndrome REGISTER

Address
0x44002064
Reset
0x00000000
Access
read only
Size
32-bit
6 fields
FieldBitsWhat it does
CTLSTAT26:24Parity vs ECC Control Status
  • 0 Calculation used ECC (i.e. programming used quad write)
  • 1 Calculation used ECC (i.e. programming used quad write)
  • 2 Calculation used ECC (i.e. programming used quad write)
  • 3 Calculation used Parity (i.e. programming used single write)
  • 4 Calculation used ECC (i.e. programming used quad write)
  • 5 Calculation used Parity (i.e. programming used single write)
  • 6 Calculation used Parity (i.e. programming used single write)
  • 7 Calculation used Parity (i.e. programming used single write)
CERR18ECC Control bit Error
  • 0 No Control bit Error (ECCSTAT either 111 or 000)
  • 1 Single Control Bit Error
DSERR17:16Double Error Detected & Single Error Corrected
  • 0 No Errors
  • 1 Single Error Corrected
  • 2 Double Error Detected
  • 3 Double Error Detected
DEDSYN15DED Syndrome
  • 0 Calculated Overall Parity Concurs with Read Overall Parity
  • 1 Calculated Overall Parity Differs from Read Overall Parity
SECSYN7:0Single Error Correction Syndrome
PERR31:28Per Word (n=3:0) Parity Error Status
  • 0 No Parity Error on Word n
  • 1 Parity Error on Word n

CRPCFM Page Read Protection REGISTER (CFM8)

Address
0x44002068
Reset
0x00C20000
Access
read/write
Size
32-bit
16 fields
FieldBitsWhat it does
CORPLOCK23Panel 1 Lock Read Protection CalOTP
  • 1 The Lock & Read Protect bits for this Page are Locked and cannot be modified
TRPLOCK22Panel 1 Lock Read Protection Test
  • 1 The Lock & Read Protect bits for this Page are Locked and cannot be modified
VSSRPLOCK121Panel 1 Lock Read Protection VSSn
  • 0 The Lock & Read Protect bits for this Page are NOT Locked and can be modified
  • 1 The Lock & Read Protect bits for this Page are Locked and cannot be modified
VSSRPLOCK020Panel 1 Lock Read Protection VSSn
  • 0 The Lock & Read Protect bits for this Page are NOT Locked and can be modified
  • 1 The Lock & Read Protect bits for this Page are Locked and cannot be modified
RCRPLOCK19Panel 1 Lock Read Protection ROMCfg
  • 0 The Lock & Read Protect bits for this Page are NOT Locked and can be modified
  • 1 The Lock & Read Protect bits for this Page are Locked and cannot be modified
BC1RPLOCK18Panel 1 Lock Read Protection BootCfg1
  • 0 The Lock & Read Protect bits for this Page are NOT Locked and can be modified
  • 1 The Lock & Read Protect bits for this Page are Locked and cannot be modified
UO1RPLOCK17Panel 1 Lock Read Protection UserOTP1
  • 1 The Lock & Read Protect bits for this Page are Locked and cannot be modified
BC1ARPLOCK16Panel 1 Lock Read Protection BootCfg1A
  • 0 The Lock & Read Protect bits for this Page are NOT Locked and can be modified
  • 1 The Lock & Read Protect bits for this Page are Locked and cannot be modified
CORP7Panel 1 Read Protect CalOTP
  • 0 Read Protection for this Page is Disabled
  • 1 Read Protection for this Page is Enabled
TRP6Panel 1 Read Protect Test
  • 0 Read Protection for this Page is Disabled
  • 1 Read Protection for this Page is Enabled
VSSRP15Panel 1 Read Protect VSSn
  • 0 Read Protection for this Page is Disabled
  • 1 Read Protection for this Page is Enabled
VSSRP04Panel 1 Read Protect VSSn
  • 0 Read Protection for this Page is Disabled
  • 1 Read Protection for this Page is Enabled
RCRP3Panel 1 Read Protect ROMCfg
  • 0 Read Protection for this Page is Disabled
  • 1 Read Protection for this Page is Enabled
BC1RP2Panel 1 Read Protect BootCfg1
  • 0 Read Protection for this Page is Disabled
  • 1 Read Protection for this Page is Enabled
UO1RP1Panel 1 Read Protect UserOTP1
  • 0 Read Protection for this Page is Disabled
BC1ARP0Panel 1 Read Protect BootCfg1A
  • 0 Read Protection for this Page is Disabled
  • 1 Read Protection for this Page is Enabled