PIC32CM5112GC00100 HMATRIX2 registers

The 44 registers of HMATRIX2 (HSB Matrix), from 0x44010000, with their reset value and every field. The PIC32CM5112GC00100 has 2253 registers in 57 peripherals, one page each.

HMATRIX2 HSB Matrix

MCFG0Master Configuration

Address
0x44010000
Reset
0x00000002
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Infinite Length
  • 1 Single Access
  • 2 Four Beat Burst
  • 3 Eight Beat Burst
  • 4 Sixteen Beat Burst

MCFG1Master Configuration

Address
0x44010004
Reset
0x00000002
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Infinite Length
  • 1 Single Access
  • 2 Four Beat Burst
  • 3 Eight Beat Burst
  • 4 Sixteen Beat Burst

MCFG2Master Configuration

Address
0x44010008
Reset
0x00000002
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Infinite Length
  • 1 Single Access
  • 2 Four Beat Burst
  • 3 Eight Beat Burst
  • 4 Sixteen Beat Burst

MCFG3Master Configuration

Address
0x4401000C
Reset
0x00000002
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Infinite Length
  • 1 Single Access
  • 2 Four Beat Burst
  • 3 Eight Beat Burst
  • 4 Sixteen Beat Burst

MCFG4Master Configuration

Address
0x44010010
Reset
0x00000002
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Infinite Length
  • 1 Single Access
  • 2 Four Beat Burst
  • 3 Eight Beat Burst
  • 4 Sixteen Beat Burst

MCFG5Master Configuration

Address
0x44010014
Reset
0x00000002
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Infinite Length
  • 1 Single Access
  • 2 Four Beat Burst
  • 3 Eight Beat Burst
  • 4 Sixteen Beat Burst

SCFG0Slave Configuration

Address
0x44010040
Reset
0x00000010
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE8:0Maximum Number of Allowed Cycles for a Burst

SCFG1Slave Configuration

Address
0x44010044
Reset
0x00000010
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE8:0Maximum Number of Allowed Cycles for a Burst

SCFG2Slave Configuration

Address
0x44010048
Reset
0x00000010
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE8:0Maximum Number of Allowed Cycles for a Burst

SCFG3Slave Configuration

Address
0x4401004C
Reset
0x00000010
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE8:0Maximum Number of Allowed Cycles for a Burst

SCFG4Slave Configuration

Address
0x44010050
Reset
0x00000010
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE8:0Maximum Number of Allowed Cycles for a Burst

SCFG5Slave Configuration

Address
0x44010054
Reset
0x00000010
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE8:0Maximum Number of Allowed Cycles for a Burst

SCFG6Slave Configuration

Address
0x44010058
Reset
0x00000010
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE8:0Maximum Number of Allowed Cycles for a Burst

SCFG7Slave Configuration

Address
0x4401005C
Reset
0x00000010
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE8:0Maximum Number of Allowed Cycles for a Burst

SCFG8Slave Configuration

Address
0x44010060
Reset
0x00000010
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE8:0Maximum Number of Allowed Cycles for a Burst

PRS0.PRASPriority A for Slave

Address
0x44010080
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
LQOSEN522Latency Quality Of Service Enable for Master 5
M5PR21:20Master 5 Priority
LQOSEN418Latency Quality Of Service Enable for Master 4
M4PR17:16Master 4 Priority
LQOSEN314Latency Quality Of Service Enable for Master 3
M3PR13:12Master 3 Priority
LQOSEN210Latency Quality Of Service Enable for Master 2
M2PR9:8Master 2 Priority
LQOSEN16Latency Quality Of Service Enable for Master 1
M1PR5:4Master 1 Priority
LQOSEN02Latency Quality Of Service Enable for Master 0
M0PR1:0Master 0 Priority

PRS1.PRASPriority A for Slave

Address
0x44010088
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
LQOSEN522Latency Quality Of Service Enable for Master 5
M5PR21:20Master 5 Priority
LQOSEN418Latency Quality Of Service Enable for Master 4
M4PR17:16Master 4 Priority
LQOSEN314Latency Quality Of Service Enable for Master 3
M3PR13:12Master 3 Priority
LQOSEN210Latency Quality Of Service Enable for Master 2
M2PR9:8Master 2 Priority
LQOSEN16Latency Quality Of Service Enable for Master 1
M1PR5:4Master 1 Priority
LQOSEN02Latency Quality Of Service Enable for Master 0
M0PR1:0Master 0 Priority

PRS2.PRASPriority A for Slave

Address
0x44010090
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
LQOSEN522Latency Quality Of Service Enable for Master 5
M5PR21:20Master 5 Priority
LQOSEN418Latency Quality Of Service Enable for Master 4
M4PR17:16Master 4 Priority
LQOSEN314Latency Quality Of Service Enable for Master 3
M3PR13:12Master 3 Priority
LQOSEN210Latency Quality Of Service Enable for Master 2
M2PR9:8Master 2 Priority
LQOSEN16Latency Quality Of Service Enable for Master 1
M1PR5:4Master 1 Priority
LQOSEN02Latency Quality Of Service Enable for Master 0
M0PR1:0Master 0 Priority

PRS3.PRASPriority A for Slave

Address
0x44010098
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
LQOSEN522Latency Quality Of Service Enable for Master 5
M5PR21:20Master 5 Priority
LQOSEN418Latency Quality Of Service Enable for Master 4
M4PR17:16Master 4 Priority
LQOSEN314Latency Quality Of Service Enable for Master 3
M3PR13:12Master 3 Priority
LQOSEN210Latency Quality Of Service Enable for Master 2
M2PR9:8Master 2 Priority
LQOSEN16Latency Quality Of Service Enable for Master 1
M1PR5:4Master 1 Priority
LQOSEN02Latency Quality Of Service Enable for Master 0
M0PR1:0Master 0 Priority

PRS4.PRASPriority A for Slave

Address
0x440100A0
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
LQOSEN522Latency Quality Of Service Enable for Master 5
M5PR21:20Master 5 Priority
LQOSEN418Latency Quality Of Service Enable for Master 4
M4PR17:16Master 4 Priority
LQOSEN314Latency Quality Of Service Enable for Master 3
M3PR13:12Master 3 Priority
LQOSEN210Latency Quality Of Service Enable for Master 2
M2PR9:8Master 2 Priority
LQOSEN16Latency Quality Of Service Enable for Master 1
M1PR5:4Master 1 Priority
LQOSEN02Latency Quality Of Service Enable for Master 0
M0PR1:0Master 0 Priority

PRS5.PRASPriority A for Slave

Address
0x440100A8
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
LQOSEN522Latency Quality Of Service Enable for Master 5
M5PR21:20Master 5 Priority
LQOSEN418Latency Quality Of Service Enable for Master 4
M4PR17:16Master 4 Priority
LQOSEN314Latency Quality Of Service Enable for Master 3
M3PR13:12Master 3 Priority
LQOSEN210Latency Quality Of Service Enable for Master 2
M2PR9:8Master 2 Priority
LQOSEN16Latency Quality Of Service Enable for Master 1
M1PR5:4Master 1 Priority
LQOSEN02Latency Quality Of Service Enable for Master 0
M0PR1:0Master 0 Priority

PRS6.PRASPriority A for Slave

Address
0x440100B0
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
LQOSEN522Latency Quality Of Service Enable for Master 5
M5PR21:20Master 5 Priority
LQOSEN418Latency Quality Of Service Enable for Master 4
M4PR17:16Master 4 Priority
LQOSEN314Latency Quality Of Service Enable for Master 3
M3PR13:12Master 3 Priority
LQOSEN210Latency Quality Of Service Enable for Master 2
M2PR9:8Master 2 Priority
LQOSEN16Latency Quality Of Service Enable for Master 1
M1PR5:4Master 1 Priority
LQOSEN02Latency Quality Of Service Enable for Master 0
M0PR1:0Master 0 Priority

PRS7.PRASPriority A for Slave

Address
0x440100B8
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
LQOSEN522Latency Quality Of Service Enable for Master 5
M5PR21:20Master 5 Priority
LQOSEN418Latency Quality Of Service Enable for Master 4
M4PR17:16Master 4 Priority
LQOSEN314Latency Quality Of Service Enable for Master 3
M3PR13:12Master 3 Priority
LQOSEN210Latency Quality Of Service Enable for Master 2
M2PR9:8Master 2 Priority
LQOSEN16Latency Quality Of Service Enable for Master 1
M1PR5:4Master 1 Priority
LQOSEN02Latency Quality Of Service Enable for Master 0
M0PR1:0Master 0 Priority

PRS8.PRASPriority A for Slave

Address
0x440100C0
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
LQOSEN522Latency Quality Of Service Enable for Master 5
M5PR21:20Master 5 Priority
LQOSEN418Latency Quality Of Service Enable for Master 4
M4PR17:16Master 4 Priority
LQOSEN314Latency Quality Of Service Enable for Master 3
M3PR13:12Master 3 Priority
LQOSEN210Latency Quality Of Service Enable for Master 2
M2PR9:8Master 2 Priority
LQOSEN16Latency Quality Of Service Enable for Master 1
M1PR5:4Master 1 Priority
LQOSEN02Latency Quality Of Service Enable for Master 0
M0PR1:0Master 0 Priority

MRCRMaster Remap Control

Address
0x44010100
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
RCB55Remap Command Bit for Master 5
  • 0 Disable remapped address decoding for master
  • 1 Enable remapped address decoding for master
RCB44Remap Command Bit for Master 4
  • 0 Disable remapped address decoding for master
  • 1 Enable remapped address decoding for master
RCB33Remap Command Bit for Master 3
  • 0 Disable remapped address decoding for master
  • 1 Enable remapped address decoding for master
RCB22Remap Command Bit for Master 2
  • 0 Disable remapped address decoding for master
  • 1 Enable remapped address decoding for master
RCB11Remap Command Bit for Master 1
  • 0 Disable remapped address decoding for master
  • 1 Enable remapped address decoding for master
RCB00Remap Command Bit for Master 0
  • 0 Disable remapped address decoding for master
  • 1 Enable remapped address decoding for master

SFR0Special Function

Address
0x44010110
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR1Special Function

Address
0x44010114
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR2Special Function

Address
0x44010118
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR3Special Function

Address
0x4401011C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR4Special Function

Address
0x44010120
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR5Special Function

Address
0x44010124
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR6Special Function

Address
0x44010128
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR7Special Function

Address
0x4401012C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR8Special Function

Address
0x44010130
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

MEIERMaster Error Interrupt Enable

Address
0x44010150
Reset
0x00000000
Access
write only
Size
32-bit
6 fields
FieldBitsWhat it does
MERR55Master 5 Access Error
MERR44Master 4 Access Error
MERR33Master 3 Access Error
MERR22Master 2 Access Error
MERR11Master 1 Access Error
MERR00Master 0 Access Error

MEIDRMaster Error Interrupt Disable

Address
0x44010154
Reset
0x00000000
Access
write only
Size
32-bit
6 fields
FieldBitsWhat it does
MERR55Master 5 Access Error
MERR44Master 4 Access Error
MERR33Master 3 Access Error
MERR22Master 2 Access Error
MERR11Master 1 Access Error
MERR00Master 0 Access Error

MEIMRMaster Error Interrupt Mask

Address
0x44010158
Reset
0x00000000
Access
read only
Size
32-bit
6 fields
FieldBitsWhat it does
MERR55Master 5 Access Error
MERR44Master 4 Access Error
MERR33Master 3 Access Error
MERR22Master 2 Access Error
MERR11Master 1 Access Error
MERR00Master 0 Access Error

MESRMaster Error Status

Address
0x4401015C
Reset
0x00000000
Access
read only
Size
32-bit
6 fields
FieldBitsWhat it does
MERR55Master 5 Access Error
MERR44Master 4 Access Error
MERR33Master 3 Access Error
MERR22Master 2 Access Error
MERR11Master 1 Access Error
MERR00Master 0 Access Error

MEAR0Master Error Address

Address
0x44010160
Reset
0x00000000
Access
read only
Size
32-bit

MEAR1Master Error Address

Address
0x44010164
Reset
0x00000000
Access
read only
Size
32-bit

MEAR2Master Error Address

Address
0x44010168
Reset
0x00000000
Access
read only
Size
32-bit

MEAR3Master Error Address

Address
0x4401016C
Reset
0x00000000
Access
read only
Size
32-bit

MEAR4Master Error Address

Address
0x44010170
Reset
0x00000000
Access
read only
Size
32-bit

MEAR5Master Error Address

Address
0x44010174
Reset
0x00000000
Access
read only
Size
32-bit