PIC32CM5112GC00100 MCLK registers

The 15 registers of MCLK (Polaris Main Clock Controller), from 0x4400A000, with their reset value and every field. The PIC32CM5112GC00100 has 2253 registers in 57 peripherals, one page each.

MCLK Polaris Main Clock Controller

INTENCLRInterrupt Enable Clear Register

Address: 0x4400A000
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CKRDY	0	Clock Ready Interrupt Enable Clear `0` The Clock Ready interrupt is disabled `1` The Clock Ready interrupt is enabled.

INTENSETInterrupt Enable Set Register

Address: 0x4400A004
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
CKRDY	0	Clock Ready Interrupt Enable Set `0` The Clock Ready interrupt is disabled. `1` The Clock Ready interrupt is enabled.

INTFLAGInterrupt Flag Status Register

Address: 0x4400A008
Reset: 0x00000001
Access: write only
Size: 32-bit

1 field

Field	Bits	What it does
CKRDY	0	Clock Ready Interrupt Flag

CLKDIV0Clock Divider Control n Register

Address: 0x4400A00C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DIV	7:0	Clock Domain n Division Factor `1` Divide by 1 `2` Divide by 2 `4` Divide by 4 `8` Divide by 8 `16` Divide by 16 `32` Divide by 32 `64` Divide by 64 `128` Divide by 128

CLKDIV1Clock Divider Control n Register

Address: 0x4400A010
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DIV	7:0	Clock Domain n Division Factor `1` Divide by 1 `2` Divide by 2 `4` Divide by 4 `8` Divide by 8 `16` Divide by 16 `32` Divide by 32 `64` Divide by 64 `128` Divide by 128

CLKDIV2Clock Divider Control n Register

Address: 0x4400A014
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
DIV	7:0	Clock Domain n Division Factor `1` Divide by 1 `2` Divide by 2 `4` Divide by 4 `8` Divide by 8 `16` Divide by 16 `32` Divide by 32 `64` Divide by 64 `128` Divide by 128

CLKMSK0Peripheral Clock Enable Mask n Register

Address: 0x4400A03C
Reset: 0x00000000
Access: read/write
Size: 32-bit

32 fields

Field	Bits	What it does
MASK30	30	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK29	29	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK28	28	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK27	27	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK26	26	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK25	25	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK24	24	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK23	23	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK22	22	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK21	21	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK20	20	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK19	19	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK18	18	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK17	17	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK16	16	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK15	15	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK14	14	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK13	13	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK12	12	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK11	11	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK10	10	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK9	9	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK8	8	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK7	7	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK6	6	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK5	5	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK4	4	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK3	3	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK2	2	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK1	1	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK0	0	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK31	31	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled

CLKMSK1Peripheral Clock Enable Mask n Register

Address: 0x4400A040
Reset: 0x00000000
Access: read/write
Size: 32-bit

32 fields

Field	Bits	What it does
MASK30	30	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK29	29	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK28	28	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK27	27	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK26	26	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK25	25	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK24	24	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK23	23	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK22	22	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK21	21	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK20	20	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK19	19	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK18	18	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK17	17	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK16	16	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK15	15	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK14	14	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK13	13	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK12	12	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK11	11	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK10	10	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK9	9	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK8	8	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK7	7	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK6	6	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK5	5	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK4	4	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK3	3	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK2	2	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK1	1	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK0	0	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK31	31	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled

CLKMSK2Peripheral Clock Enable Mask n Register

Address: 0x4400A044
Reset: 0x00000000
Access: read/write
Size: 32-bit

32 fields

Field	Bits	What it does
MASK30	30	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK29	29	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK28	28	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK27	27	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK26	26	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK25	25	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK24	24	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK23	23	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK22	22	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK21	21	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK20	20	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK19	19	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK18	18	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK17	17	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK16	16	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK15	15	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK14	14	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK13	13	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK12	12	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK11	11	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK10	10	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK9	9	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK8	8	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK7	7	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK6	6	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK5	5	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK4	4	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK3	3	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK2	2	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK1	1	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK0	0	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK31	31	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled

CLKMSK3Peripheral Clock Enable Mask n Register

Address: 0x4400A048
Reset: 0x00000000
Access: read/write
Size: 32-bit

32 fields

Field	Bits	What it does
MASK30	30	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK29	29	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK28	28	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK27	27	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK26	26	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK25	25	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK24	24	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK23	23	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK22	22	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK21	21	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK20	20	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK19	19	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK18	18	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK17	17	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK16	16	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK15	15	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK14	14	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK13	13	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK12	12	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK11	11	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK10	10	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK9	9	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK8	8	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK7	7	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK6	6	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK5	5	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK4	4	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK3	3	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK2	2	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK1	1	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK0	0	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK31	31	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled

CLKMSK4Peripheral Clock Enable Mask n Register

Address: 0x4400A04C
Reset: 0x00000000
Access: read/write
Size: 32-bit

32 fields

Field	Bits	What it does
MASK30	30	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK29	29	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK28	28	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK27	27	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK26	26	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK25	25	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK24	24	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK23	23	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK22	22	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK21	21	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK20	20	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK19	19	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK18	18	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK17	17	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK16	16	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK15	15	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK14	14	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK13	13	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK12	12	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK11	11	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK10	10	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK9	9	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK8	8	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK7	7	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK6	6	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK5	5	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK4	4	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK3	3	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK2	2	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK1	1	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK0	0	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK31	31	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled

CLKMSK5Peripheral Clock Enable Mask n Register

Address: 0x4400A050
Reset: 0x00000000
Access: read/write
Size: 32-bit

32 fields

Field	Bits	What it does
MASK30	30	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK29	29	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK28	28	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK27	27	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK26	26	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK25	25	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK24	24	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK23	23	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK22	22	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK21	21	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK20	20	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK19	19	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK18	18	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK17	17	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK16	16	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK15	15	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK14	14	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK13	13	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK12	12	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK11	11	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK10	10	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK9	9	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK8	8	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK7	7	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK6	6	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK5	5	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK4	4	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK3	3	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK2	2	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK1	1	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK0	0	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK31	31	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled

CLKMSK6Peripheral Clock Enable Mask n Register

Address: 0x4400A054
Reset: 0x00000000
Access: read/write
Size: 32-bit

32 fields

Field	Bits	What it does
MASK30	30	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK29	29	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK28	28	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK27	27	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK26	26	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK25	25	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK24	24	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK23	23	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK22	22	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK21	21	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK20	20	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK19	19	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK18	18	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK17	17	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK16	16	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK15	15	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK14	14	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK13	13	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK12	12	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK11	11	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK10	10	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK9	9	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK8	8	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK7	7	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK6	6	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK5	5	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK4	4	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK3	3	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK2	2	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK1	1	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK0	0	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK31	31	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled

CLKMSK7Peripheral Clock Enable Mask n Register

Address: 0x4400A058
Reset: 0x00000000
Access: read/write
Size: 32-bit

32 fields

Field	Bits	What it does
MASK30	30	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK29	29	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK28	28	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK27	27	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK26	26	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK25	25	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK24	24	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK23	23	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK22	22	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK21	21	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK20	20	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK19	19	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK18	18	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK17	17	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK16	16	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK15	15	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK14	14	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK13	13	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK12	12	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK11	11	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK10	10	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK9	9	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK8	8	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK7	7	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK6	6	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK5	5	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK4	4	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK3	3	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK2	2	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK1	1	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK0	0	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK31	31	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled

CLKMSK8Peripheral Clock Enable Mask n Register

Address: 0x4400A05C
Reset: 0x00000000
Access: read/write
Size: 32-bit

32 fields

Field	Bits	What it does
MASK30	30	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK29	29	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK28	28	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK27	27	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK26	26	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK25	25	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK24	24	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK23	23	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK22	22	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK21	21	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK20	20	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK19	19	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK18	18	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK17	17	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK16	16	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK15	15	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK14	14	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK13	13	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK12	12	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK11	11	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK10	10	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK9	9	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK8	8	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK7	7	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK6	6	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK5	5	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK4	4	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK3	3	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK2	2	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK1	1	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK0	0	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled
MASK31	31	Peripheral Clock Enable Mask `0` Peripheral clock mclk_clk_periph[n32+x] stopped `1` Peripheral clock mclk_clk_periph[n32+x] enabled