The 58 registers of SERCOM3 (Serial Communication Interface), from 0x4480E000, with their reset value and every field. The PIC32CM5112GC00100 has 2253 registers in 57 peripherals, one page each.
SERCOM3 Serial Communication Interface
I2CM.CTRLAI2CM Control A
Address
0x4480E000
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
Field
Bits
What it does
LOWTOUTEN
30
SCL Low Timeout Enable
INACTOUT
29:28
Inactive Time-Out
0 Disable
1 5-6 SCL cycle time-out
2 10-11 SCL cycle time-out
3 20-21-6 SCL cycle time-out
SCLSM
27
SCL Clock Stretch Mode
SPEED
25:24
Transfer Speed
0 Standard-Mode (SM) and Fast-Mode (FM)
1 Fast-Mode Plus (FM+)
2 High-Speed Mode
SEXTTOEN
23
Slave SCL Low Extend Timeout
MEXTTOEN
22
Master SCL Low Extend Timeout
SDAHOLD
21:20
SDA Hold Time
0 Disable
1 50ns - 100ns hold time
2 300ns - 600ns hold time
3 400ns - 800ns hold time
SMBUSEN
17
SMBUS Input Buffer Enable
PINOUT
16
Pin Usage
SLEWRATE
11:10
Slew Rate Selection
0 Standard mode
1 Fast mode
2 Fast mode plus
3 High-speed mode
FILTSEL
9:8
Input Filter Selection
0 Disable
2 Minimum 50ns filter
3 Minimum 10ns filter
RUNSTDBY
7
Run in Standby
MODE
4:2
Operating Mode
5 I2C host mode operation
ENABLE
1
Enable
SWRST
0
Software Reset
I2CS.CTRLAI2CS Control A
Address
0x4480E000
Reset
0x00000000
Access
read/write
Size
32-bit
13 fields
Field
Bits
What it does
LOWTOUTEN
30
SCL Low Timeout Enable
SCLSM
27
SCL Clock Stretch Mode
SPEED
25:24
Transfer Speed
0 Standard-Mode (SM) and Fast-Mode (FM)
1 Fast-Mode Plus (FM+)
2 High-Speed Mode
SEXTTOEN
23
Slave SCL Low Extend Timeout
SDAHOLD
21:20
SDA Hold Time
0 Disable
1 50ns - 100ns hold time
2 300ns - 600ns hold time
3 400ns - 800ns hold time
SMBUSEN
17
SMBUS Input Buffer Enable
PINOUT
16
Pin Usage
SLEWRATE
11:10
Slew Rate Selection
0 Standard mode
1 Fast mode
2 Fast mode plus
3 High-speed mode
FILTSEL
9:8
Input Filter Selection
RUNSTDBY
7
Run during Standby
MODE
4:2
Operating Mode
4 I2C client mode operation
ENABLE
1
Enable
SWRST
0
Software Reset
SPI.CTRLASPI Control A
Address
0x4480E000
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
DORD
30
Data Order
0 MSB is transmitted first
1 LSB is transmitted first
CPOL
29
Clock Polarity
0 SCK is low when idle
1 SCK is high when idle
CPHA
28
Clock Phase
0 The data is sampled on a leading SCK edge and changed on a trailing SCK edge
1 The data is sampled on a trailing SCK edge and changed on a leading SCK edge
FORM
27:24
Frame Format
0 SPI frame
2 SPI frame with address
DIPO
21:20
Data In Pinout
0 SERCOM PAD0 is used as data input
1 SERCOM PAD1 is used as data input
2 SERCOM PAD2 is used as data input
3 SERCOM PAD3 is used as data input
DOPO
17:16
Data Out Pinout
0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2]
2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2]
IBON
8
Immediate Buffer Overflow Notification
RUNSTDBY
7
Run during Standby
MODE
4:2
Operating Mode
2 SPI slave operation
3 SPI master operation
ENABLE
1
Enable
SWRST
0
Software Reset
USART.CTRLAUSART Control A
Address
0x4480E000
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
Field
Bits
What it does
DORD
30
Data Order
0 MSB is transmitted first.
1 LSB is transmitted first.
CPOL
29
Clock Polarity
CMODE
28
Communication Mode
0 Asynchronous communication.
1 Synchronous communication.
FORM
27:24
Frame Format
0 USART frame
1 USART frame with parity
2 LIN Master Break and Synck generation
4 LIN Slave break detection and auto-baud
5 Break detection and auto-baud with parity
SAMPA
23:22
Sample Adjustment
RXPO
21:20
Receive Data Pinout
0 SERCOM PAD0 is used for data reception
1 SERCOM PAD1 is used for data reception
2 SERCOM PAD2 is used for data reception
3 SERCOM PAD3 is used for data reception
TXPO
17:16
Transmit Data Pinout
0 PAD[0] = TxD; PAD[1] = XCK
2 PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS
3 PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE
SAMPR
15:13
Sample
0 16x oversampling using arithmetic baud rate generation
1 16x oversampling using fractional baud rate generation
2 8x oversampling using arithmetic baud rate generation
3 8x oversampling using fractional baud rate generation
4 3x oversampling using arithmetic baud rate generation
RXINV
10
Receive Data Invert
0 RxD is not inverted
1 RxD is inverted
TXINV
9
Transmit Data Invert
0 TxD is not inverted
1 TxD is inverted
IBON
8
Immediate Buffer Overflow Notification
RUNSTDBY
7
Run during Standby
MODE
4:2
Operating Mode
0 USART with external clock
1 Usart with internal clock
ENABLE
1
Enable
SWRST
0
Software Reset
I2CM.CTRLBI2CM Control B
Address
0x4480E004
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
FIFOCLR
23:22
FIFO Clear
0 No action
1 Clear TX FIFO
2 Clear RX FIFO
3 Clear both TX and RF FIFOs
ACKACT
18
Acknowledge Action
CMD
17:16
Command
QCEN
9
Quick Command Enable
SMEN
8
Smart Mode Enable
I2CS.CTRLBI2CS Control B
Address
0x4480E004
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
FIFOCLR
23:22
FIFO Clear
0 No action
1 Clear TX FIFO
2 Clear RX FIFO
3 Clear both TX and RF FIFOs
ACKACT
18
Acknowledge Action
CMD
17:16
Command
AMODE
15:14
Address Mode
0 The slave responds to the address written in ADDR.ADDR masked by the value in ADDR.ADDRMASK
1 The slave responds to the two unique addresses in ADDR and ADDRMASK
2 The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit
AACKEN
10
Automatic Address Acknowledge
GCMD
9
PMBus Group Command
SMEN
8
Smart Mode Enable
SPI.CTRLBSPI Control B
Address
0x4480E004
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
FIFOCLR
23:22
FIFO Clear
0 No action
1 Clear TX FIFO
2 Clear RX FIFO
3 Clear both TX and RF FIFOs
RXEN
17
Receiver Enable
AMODE
15:14
Address Mode
0 ADDRMASK is used as a mask to the AADR register
1 The slave responds to the two unique addresses in ADDR and ADDRMASK
2 The slave responds to the range of addresses between and including ADDR and ADDRMASK. ADDR is the upper limit
MSSEN
13
Master Slave Select Enable
0 Hardware SS control is disabled
1 Hardware SS control is enabled
SSDE
9
Slave Select Low Detect Enable
0 SS low detector is disabled
1 SS low detector is enabled
PLOADEN
6
Data Preload Enable
CHSIZE
2:0
Character Size
0 8-bits character
1 9-bits character
USART.CTRLBUSART Control B
Address
0x4480E004
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
Field
Bits
What it does
LINCMD
25:24
LIN Command
0 Normal USART transmission
1 Break field is transmitted when DATA is written
2 Break, synch and identifier are automaticcaly transmitted when DATA is written with the identifier
FIFOCLR
23:22
FIFO Clear
0 No action
1 Clear TX FIFO
2 Clear RX FIFO
3 Clear both TX and RF FIFOs
RXEN
17
Receiver Enable
TXEN
16
Transmitter Enable
PMODE
13
Parity Mode
0 Even parity
1 Odd parity
ENC
10
Encoding Format
0 Data is not encoded
1 Data is IrDA encoded
SFDE
9
Start of Frame Detection Enable
COLDEN
8
Collision Detection Enable
SBMODE
6
Stop Bit Mode
0 One stop bit
1 Two stop bits
CHSIZE
2:0
Character Size
0 8-bits character
1 9-bits character
5 5-bits character
6 6-bits character
7 7-bits character
I2CM.CTRLCI2CM Control C
Address
0x4480E008
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
RXTRHOLD
29:28
Receive FIFO Threshold
0 Interrupt and DMA triggers are generated when DATA is present in the FIFO
1 Interrupt and DMA triggers are generated when FIFO is half-full
2 Interrupt and DMA triggers are generated when FIFO is full
FIFOEN
27
FIFO Enable
DATA32B
24
Data 32 Bit
TXTRHOLD
31:30
Transmit FIFO Threshold
0 Interrupt and DMA triggers are generated as long as the FIFO is not full
1 Interrupt and DMA triggers are generated when half FIFO space is free
2 Interrupt and DMA triggers are generated as long as the FIFO is not full
I2CS.CTRLCI2CS Control C
Address
0x4480E008
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
RXTRHOLD
29:28
Receive FIFO Threshold
0 Interrupt and DMA triggers are generated when DATA is present in the FIFO
1 Interrupt and DMA triggers are generated when FIFO is half-full
2 Interrupt and DMA triggers are generated when FIFO is full
FIFOEN
27
FIFO Enable
DATA32B
24
Data 32 Bit
SDASETUP
3:0
SDA Setup Time
TXTRHOLD
31:30
Transmit FIFO Threshold
0 Interrupt and DMA triggers are generated as long as the FIFO is not full
1 Interrupt and DMA triggers are generated when half FIFO space is free
2 Interrupt and DMA triggers are generated as long as the FIFO is not full
SPI.CTRLCSPI Control C
Address
0x4480E008
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
RXTRHOLD
29:28
Receive FIFO Threshold
0 Interrupt and DMA triggers are generated when DATA is present in the FIFO
1 Interrupt and DMA triggers are generated when FIFO is half-full
2 Interrupt and DMA triggers are generated when FIFO is full
FIFOEN
27
FIFO Enable
DATA32B
24
Data 32 Bit
FMODE
17
Frame mode
0 Frame Master
1 Frame Slave
FRMEN
16
Frame mode enable
IGNTUR
11
Ignore Transmit Underrun
FSPOL
10
Frame Synch Polarity
0 VCC-level valid polarity
1 GND-level valid polarity
FSLEN
9
Frame Synch Length
0 One SCK pulse
1 One frame duration
FSES
8
Frame Synch Edge Select
ICSPACE
5:0
Inter-Character Spacing
TXTRHOLD
31:30
Transmit FIFO Threshold
0 Interrupt and DMA triggers are generated as long as the FIFO is not full
1 Interrupt and DMA triggers are generated when half FIFO space is free
2 Interrupt and DMA triggers are generated as long as the FIFO is empty
USART.CTRLCUSART Control C
Address
0x4480E008
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
Field
Bits
What it does
RXTRHOLD
29:28
Receive FIFO Threshold
0 Interrupt and DMA triggers are generated when DATA is present in the FIFO
1 Interrupt and DMA triggers are generated when FIFO is half-full
2 Interrupt and DMA triggers are generated when FIFO is full
FIFOEN
27
FIFO Enable
DATA32B
25:24
Data 32 Bit
MAXITER
22:20
Maximum Iterations
DSNACK
17
Disable Successive NACK
INACK
16
Inhibit Not Acknowledge
HDRDLY
11:10
LIN Master Header Delay
0 Delay between break and sync transmission is 1-bit time
1 Delay between break and sync transmission is 4-bit time
2 Delay between break and sync transmission is 8-bit time
3 Delay between break and sync transmission is 14-bit time
BRKLEN
9:8
LIN Master Break Length
0 Break field transmission is 13 bit times
1 Break field transmission is 17 bit times
2 Break field transmission is 21 bit times
3 Break field transmission is 26 bit times
GTIME
2:0
Guard Time
TXTRHOLD
31:30
Transmit FIFO Threshold
0 Interrupt and DMA triggers are generated as long as the FIFO is not full
1 Interrupt and DMA triggers are generated when half FIFO space is free
2 Interrupt and DMA triggers are generated when the FIFO is empty
I2CM.BAUDI2CM Baud Rate
Address
0x4480E00C
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
HSBAUD
23:16
High Speed Baud Rate Value
BAUDLOW
15:8
Baud Rate Value Low
BAUD
7:0
Baud Rate Value
HSBAUDLOW
31:24
High Speed Baud Rate Value Low
SPI.BAUDSPI Baud Rate
Address
0x4480E00C
Reset
0x00
Access
read/write
7BAUD7
6BAUD6
5BAUD5
4BAUD4
3BAUD3
2BAUD2
1BAUD1
0BAUD0
1 field
Field
Bits
What it does
BAUD
7:0
Baud Rate Value
USART.BAUDUSART Baud Rate
Address
0x4480E00C
Reset
0x0000
Access
read/write
Size
16-bit
3 fields
Field
Bits
What it does
BAUD
15:0
Baud Rate Value
FP
15:13
Fractional Part
BAUD
12:0
Baud Rate Value
USART.RXPLUSART Receive Pulse Length
Address
0x4480E00E
Reset
0x00
Access
read/write
7RXPL7
6RXPL6
5RXPL5
4RXPL4
3RXPL3
2RXPL2
1RXPL1
0RXPL0
1 field
Field
Bits
What it does
RXPL
7:0
Receive Pulse Length
I2CM.INTENCLRI2CM Interrupt Enable Clear
Address
0x4480E014
Reset
0x00
Access
read/write
7ERROR
6–
5–
4RXFF
3TXFE
2–
1SB
0MB
5 fields
Field
Bits
What it does
ERROR
7
Combined Error Interrupt Disable
RXFF
4
Rx FIFO Full Interrupt Disable
TXFE
3
Tx FIFO Empty Interrupt Disable
SB
1
Slave On Bus Interrupt Disable
MB
0
Master On Bus Interrupt Disable
I2CS.INTENCLRI2CS Interrupt Enable Clear
Address
0x4480E014
Reset
0x00
Access
read/write
7ERROR
6–
5–
4RXFF
3TXFE
2DRDY
1AMATCH
0PREC
6 fields
Field
Bits
What it does
ERROR
7
Combined Error Interrupt Disable
RXFF
4
Rx FIFO Full Interrupt Disable
TXFE
3
Tx FIFO Empty Interrupt Disable
DRDY
2
Data Interrupt Disable
AMATCH
1
Address Match Interrupt Disable
PREC
0
Stop Received Interrupt Disable
SPI.INTENCLRSPI Interrupt Enable Clear
Address
0x4480E014
Reset
0x00
Access
read/write
7ERROR
6–
5–
4–
3SSL
2RXC
1TXC
0DRE
5 fields
Field
Bits
What it does
ERROR
7
Combined Error Interrupt Disable
SSL
3
Slave Select Low Interrupt Disable
RXC
2
Receive Complete Interrupt Disable
TXC
1
Transmit Complete Interrupt Disable
DRE
0
Data Register Empty Interrupt Disable
USART.INTENCLRUSART Interrupt Enable Clear
Address
0x4480E014
Reset
0x00
Access
read/write
7ERROR
6–
5RXBRK
4CTSIC
3RXS
2RXC
1TXC
0DRE
7 fields
Field
Bits
What it does
ERROR
7
Combined Error Interrupt Disable
RXBRK
5
Break Received Interrupt Disable
CTSIC
4
Clear To Send Input Change Interrupt Disable
RXS
3
Receive Start Interrupt Disable
RXC
2
Receive Complete Interrupt Disable
TXC
1
Transmit Complete Interrupt Disable
DRE
0
Data Register Empty Interrupt Disable
I2CM.INTENSETI2CM Interrupt Enable Set
Address
0x4480E016
Reset
0x00
Access
read/write
7ERROR
6–
5–
4RXFF
3TXFE
2–
1SB
0MB
5 fields
Field
Bits
What it does
ERROR
7
Combined Error Interrupt Enable
RXFF
4
Rx FIFO Full Interrupt Enable
TXFE
3
Tx FIFO Empty Interrupt Enable
SB
1
Slave On Bus Interrupt Enable
MB
0
Master On Bus Interrupt Enable
I2CS.INTENSETI2CS Interrupt Enable Set
Address
0x4480E016
Reset
0x00
Access
read/write
7ERROR
6–
5–
4RXFF
3TXFE
2DRDY
1AMATCH
0PREC
6 fields
Field
Bits
What it does
ERROR
7
Combined Error Interrupt Enable
RXFF
4
Rx FIFO Full Interrupt Enable
TXFE
3
Tx FIFO Empty Interrupt Enable
DRDY
2
Data Interrupt Enable
AMATCH
1
Address Match Interrupt Enable
PREC
0
Stop Received Interrupt Enable
SPI.INTENSETSPI Interrupt Enable Set
Address
0x4480E016
Reset
0x00
Access
read/write
7ERROR
6–
5–
4–
3SSL
2RXC
1TXC
0DRE
5 fields
Field
Bits
What it does
ERROR
7
Combined Error Interrupt Enable
SSL
3
Slave Select Low Interrupt Enable
RXC
2
Receive Complete Interrupt Enable
TXC
1
Transmit Complete Interrupt Enable
DRE
0
Data Register Empty Interrupt Enable
USART.INTENSETUSART Interrupt Enable Set
Address
0x4480E016
Reset
0x00
Access
read/write
7ERROR
6–
5RXBRK
4CTSIC
3RXS
2RXC
1TXC
0DRE
7 fields
Field
Bits
What it does
ERROR
7
Combined Error Interrupt Enable
RXBRK
5
Break Received Interrupt Enable
CTSIC
4
Clear To Send Input Change Interrupt Enable
RXS
3
Receive Start Interrupt Enable
RXC
2
Receive Complete Interrupt Enable
TXC
1
Transmit Complete Interrupt Enable
DRE
0
Data Register Empty Interrupt Enable
I2CM.INTFLAGI2CM Interrupt Flag Status and Clear
Address
0x4480E018
Reset
0x00
Access
read/write
7ERROR
6–
5–
4RXFF
3TXFE
2–
1SB
0MB
5 fields
Field
Bits
What it does
ERROR
7
Combined Error Interrupt
RXFF
4
Rx FIFO Full Interrupt
TXFE
3
Tx FIFO Empty Interrupt
SB
1
Slave On Bus Interrupt
MB
0
Master On Bus Interrupt
I2CS.INTFLAGI2CS Interrupt Flag Status and Clear
Address
0x4480E018
Reset
0x00
Access
read/write
7ERROR
6–
5–
4RXFF
3TXFE
2DRDY
1AMATCH
0PREC
6 fields
Field
Bits
What it does
ERROR
7
Combined Error Interrupt
RXFF
4
Rx FIFO Full Interrupt
TXFE
3
Tx FIFO Empty Interrupt
DRDY
2
Data Interrupt
AMATCH
1
Address Match Interrupt
PREC
0
Stop Received Interrupt
SPI.INTFLAGSPI Interrupt Flag Status and Clear
Address
0x4480E018
Reset
0x00
Access
read/write
7ERROR
6–
5–
4–
3SSL
2RXC
1TXC
0DRE
5 fields
Field
Bits
What it does
ERROR
7
Combined Error Interrupt
SSL
3
Slave Select Low Interrupt Flag
RXC
2
Receive Complete Interrupt
TXC
1
Transmit Complete Interrupt
DRE
0
Data Register Empty Interrupt
USART.INTFLAGUSART Interrupt Flag Status and Clear
BETA