PIC32CM5112SG00064 CoreDebug_NS registers

The 4 registers of CoreDebug_NS (Debug Control Block), from 0xE002EDF0, with their reset value and every field. The PIC32CM5112SG00064 has 3618 registers in 68 peripherals, one page each.

CoreDebug_NS Debug Control Block

DHCSRDebug Halting Control and Status Register

Address
0xE002EDF0
Reset
0x00000000
Access
read/write
Size
32-bit
13 fields
FieldBitsWhat it does
S_RESTART_ST26Restart sticky status
S_RESET_ST25Reset sticky status
S_RETIRE_ST24Retire sticky status
S_SDE20Secure debug enabled
S_LOCKUP19Lockup status
S_SLEEP18Sleeping status
S_HALT17Halted status
S_REGRDY16Register ready status
S_SNAPSTALL5Snap stall control
C_MASKINTS3Mask PendSV, SysTick and external configurable interrupts
C_STEP2Enable single step
C_HALT1Halt processor
C_DEBUGEN0Enable Halting debug

DCRSRDebug Core Register Select Register

Address
0xE002EDF4
Reset
0x00000000
Access
write only
Size
32-bit
2 fields
FieldBitsWhat it does
REGWnR16Register write/not-read access
REGSEL6:0Register selector

DEMCRDebug Exception and Monitor Control Register

Address
0xE002EDFC
Reset
0x00000000
Access
read/write
Size
32-bit
15 fields
FieldBitsWhat it does
TRCENA24Global DWT and ITM features enable
SDME20Secure DebugMonitor enable
MON_REQ19DebugMonitor semaphore bit
MON_STEP18Enable DebugMonitor stepping
MON_PEND17DebugMonitor pending state
MON_EN16DebugMonitor enable
VC_SFERR11SecureFault exception Halting debug vector catch enable
VC_HARDERR10HardFault exception Halting debug vector catch enable
VC_INTERR9Excception entry and return faults Halting debug vector catch enable
VC_BUSERR8BusFault exception Halting debug vector catch enable
VC_STATERR7UsageFault exception state information error Halting debug vector catch enable
VC_CHKERR6UsageFault exception checking error Halting debug vector catch enable
VC_NOCPERR5UsageFault exception coprocessor access Halting debug vector catch enable
VC_MMERR4MemManage exception Halting debug vector catch enable
VC_CORERESET0Core reset Halting debug vector catch enable

DSCSRDebug Security Control and Status Register

Address
0xE002EE08
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
CDSKEY17CDS field write-enable key
CDS16Current domain Secure
SBRSEL1Secure Banked register select
SBRSELEN0Secure Banked register select enable