The 29 registers of PUF (Physically Unclonable Function), from 0x44834000, with their reset value and every field. The PIC32CM5112SG00064 has 3618 registers in 68 peripherals, one page each.
PUF Physically Unclonable Function
CTRLAControl Register A
Address
0x44834000
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
RUNSTDBY
6
RUNSTDBY Enable bit - not used by EIP HWWriting this register has no affect on the EIPNote: Currently this bit is present, but has no functionality. This bit is part of the IP wrapper but has no use for the EIP.
PRIV
2
Privileged Access Only
0 PUF registers accessible in privileged and unprivileged modes.
1 PUF registers only accessible in privileged mode.
ENABLE
1
Clock Enable bit
0 PUF clock is disabled and Macro held in reset and any access to QK register would cause PSLVERR.
1 PUF clock is enabled.
SWRST
0
Software ResetNOTE: Reset to PUF must be held active long enough to reset complete macro.
0 No effect
1 Reset registers and internal state
STATUSAStatus Register A
Address
0x44834038
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
BUSY
0
PUF Busy indicator
0 Macro can accept commands.
1 Macro has not completed the power up or power down sequence and cannot accept any other commands.
DISABLEDisable Function Control Register
Address
0x44834100
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
TEST_MEM
30
TEST_MEMORY Command Disable bit
0 Command is enabled.
1 Command is disabled.
SKIP_MEM_TEST
29
SKIP_MEMORY TEST Command Control bit
0 Command is enabled / Not Skipped.
1 Command is disabled / Skipped during initialization
GEN_RAND
15
GENERATE_RANDOM Command Disable bit
0 Command is enabled.
1 Command is disabled.
WRAP
9
WRAP Command Disable bit
0 Command is enabled.
1 Command is disabled.
WRAP_GEN_RAND
8
WRAP_GENERATE_RANDOM Command Disable bit
0 Command is enabled.
1 Command is disabled.
UNWRAP
7
UNWRAP Command Disable bit
0 Command is enabled.
1 Command is disabled.
GET_KEY
6
GET_KEY Command Disable bit
0 Command is enabled.
1 Command is disabled.
STOP
5
STOP Command Disable bit
0 Command is enabled.
1 Command is disabled.
RECONSTRUCT
3
RECONSTRUCT Command Disable bit
0 Command is enabled.
1 Command is disabled.
START
2
START Command Disable bit
0 Command is enabled.
1 Command is disabled.
ENROLL
1
ENROLL Command Disable bit
0 Command is enabled.
1 Command is disabled.
TEST_PUF
31
TEST_PUF Command Disable bit
0 Command is enabled.
1 Command is disabled.
RESTRICT0Restrict User Context 0 Control Register
Address
0x44834104
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RESTRICT_CONTEXT_0
31:0
Restrict User Context Writing a 1 in a bit position prevents other PUF keys to be generated with this context bit set. NOTE: Refer to the EIP datasheet for the function of the restrict_user_context signals
RESTRICT1Restrict User Context 1 Control Register
Address
0x44834108
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RESTRICT_CONTEXT_1
31:0
Restrict User Context Writing a 1 in a bit position prevents other PUF keys to be generated with this context bit set. NOTE: Refer to the EIP datasheet for the function of the restrict_user_context signals
CTRL_PWRPower Control Register
Address
0x4483410C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
SRAM_PWRSW
0
SRAM Power Switch Enable Bit
0 SRAM register power is disabled ( puf_req_power_sram driven to 0)
1 SRAM register power is enabled ( puf_req_power_sram driven to 1)
CTRL_KEYKEY Control Register
Address
0x44834110
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CLR_PUF_KEY
0
Clear PUF Key Control Bit
0 NO Affect
1 Clears the following outputs from this macro - puf_key, puf_valid, puf_index
QK_CRControl register; The Control register defines which command must be executed next. When the command is accepted or rejected, the bits automatically revert to 0. Only one command bit may be written wi
Address
0x44834200
Reset
0x00000000
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
qk_test_memory
30
Begin Test Memory operation
qk_generate_random
15
Begin Generate Random operation
qk_wrap
9
Begin Wrap operation
qk_wrap_generated_random
8
Begin Wrap Generated Random operation
qk_unwrap
7
Begin Unwrap operation
qk_get_key
6
Begin Get Key operation
qk_stop
5
Begin Stop operation
qk_reconstruct
3
Begin Reconstruct operation
qk_start
2
Begin Start operation
qk_enroll
1
Begin Enroll operation
qk_zeroize
0
Begin Zeroize operation
qk_test_puf
31
Begin Test PUF operation
QK_ORROperation Result register; The Operation Result register provides the result code of the last operation (Initialization, Generate Random, etc.). The value in this register is only valid when qk_busy =
Address
0x44834204
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
qk_result_code
7:0
Result code of last operation
0
240
241
242
243
244
245
246
247
248
255
qk_last_operation
31:24
Number of last operation
0
1
2
3
5
6
7
8
9
15
30
31
32
47
QK_SRStatus register; The Status register shows the current status of QuiddiKey and indicates whether a data transfer is requested.
Address
0x44834208
Reset
0x00000001
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
qk_do_request
6
Request for data out transfer via the QK_DOR register
qk_di_request
5
Request for data in transfer via the QK_DIR register
qk_rejected
4
Read: Last command was rejected Write 1: Clears this bit
qk_zeroized
3
QuiddiKey is in Zeroized or Locked state
qk_error
2
Last operation failed
qk_ok
1
Last operation was successful
qk_busy
0
Operation is in progress
QK_ARAllow register; The Allow register indicates which operations are currently allowed.
Address
0x4483420C
Reset
0x00000000
Access
read only
Size
32-bit
11 fields
Field
Bits
What it does
qk_allow_test_memory
30
0: Test Memory operation is not allowed 1: Test Memory operation is allowed
qk_allow_generate_random
15
0: Generate Random operation is not allowed 1: Generate Random operation is allowed
qk_allow_wrap
9
0: Wrap operation is not allowed 1: Wrap operation is allowed
qk_allow_wrap_generated_random
8
0: Wrap Generated Random operation is not allowed 1: Wrap Generated Random operation is allowed
qk_allow_unwrap
7
0: Unwrap operation is not allowed 1: Unwrap operation is allowed
qk_allow_get_key
6
0: Get Key operation is not allowed 1: Get Key operation is allowed
qk_allow_stop
5
0: Stop operation is not allowed 1: Stop operation is allowed
qk_allow_reconstruct
3
0: Reconstruct operation is not allowed 1: Reconstruct operation is allowed
qk_allow_start
2
0: Start operation is not allowed 1: Start operation is allowed
qk_allow_enroll
1
0: Enroll operation is not allowed 1: Enroll operation is allowed
qk_allow_test_puf
31
0: Test PUF operation is not allowed 1: Test PUF operation is allowed
QK_IERInterrupt Enable register; With the Interrupt Enable register all QuiddiKey interrupts can be enabled or disabled, without changing the Interrupt Mask register.
Address
0x44834210
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
qk_int_en
0
0: Disables all QuiddiKey interrupts 1: Enables all QuiddiKey interrupts that are enabled in the Interrupt Mask register
QK_IMRInterrupt Mask register; Individual QuiddiKey interrupts can be enabled or disabled with the Interrupt Mask register.
Address
0x44834214
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
qk_int_en_do_request
6
Enables the data out request interrupt
qk_int_en_di_request
5
Enables the data in request interrupt
qk_int_en_rejected
4
Enables the rejected interrupt
qk_int_en_zeroized
3
Enables the zeroized interrupt
qk_int_en_error
2
Enables the error interrupt
qk_int_en_ok
1
Enables the ok interrupt
qk_int_en_busy
0
Enables the busy interrupt
QK_ISRInterrupt Status register; The Interrupt Status register indicates which interrupt has occurred. Multiple interrupts may occur at the same time (e.g. the busy interrupt occurs together with one of the
Address
0x44834218
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
qk_int_do_request
6
A positive edge has occurred on qk_do_request, which means that a data out transfer is requested via the QK_DOR register
qk_int_di_request
5
A positive edge has occurred on qk_di_request, which means that a data in transfer is requested via the QK_DIR register
qk_int_rejected
4
A positive edge has occurred on qk_rejected, which means that a command was rejected
qk_int_zeroized
3
A positive edge has occurred on qk_zeroized, which means that QuiddiKey has moved to the Zeroized or Locked state
qk_int_error
2
A positive edge has occurred on qk_error, which means that an operation has failed
qk_int_ok
1
A positive edge has occurred on qk_ok, which means that an operation successfully completed
qk_int_busy
0
A negative edge has occurred on qk_busy, which means that an operation has completed
QK_DATA_DESTData Destination register; The Data Destination register defines via which interface data is made available by QuiddiKey. Only one bit at a time may be 1.
Address
0x44834220
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
qk_dest_so
1
Data will be made available via the SO interface
qk_dest_dor
0
Data will be made available via the QK_DOR register
QK_DATA_SRCData Source register; The Data Source register defines via which interface data must be provided to QuiddiKey. Combinations of bits may be 1 at a time.
Address
0x44834224
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
qk_src_si
1
Data must be provided via the SI interface
qk_src_dir
0
Data must be provided via the QK_DIR register
QK_KEY_INDEXKey Index register; The Key Index register provides the index of the key that is currently output.
Address
0x44834228
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
qk_key_inde
3:0
Value of the Key Index
QK_DIRData Input register; The Data Input register is used to transfer data to QuiddiKey. It can only be written when input data is requested (indicated by the qk_di_request signal). When written at any oth
Address
0x448342A0
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
qk_di
31:0
Input data to QuiddiKey
QK_DORData Output register; The Data Output register is used to transfer data from QuiddiKey. It can only be read when input data is available (indicated by the qk_do_request signal). When read at any other
Address
0x448342A8
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
qk_do
31:0
Output data from QuiddiKey
QK_MISCMiscellaneous register; The Miscellaneous register defines miscellaneous settings for QuiddiKey. These usually need to be configured only once after power up orreset.
Address
0x448342C0
Reset
0x00000001
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
qk_data_endianness
0
Defines the endianness of data in QK_DIR and QK_DOR: 0: Little endian 1: Big endian (default)
QK_IF_SRInterface Status register; The status of the interface can be monitored with the Interface Status register. Writing 1 to a bit, clears the corresponding bit.
Address
0x448342D0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
reg_if_error
0
An error has occurred at the register interface
QK_TESTTest register; With the Test register a BIST can be started. It also shows the result of the last BIST.
Address
0x448342D8
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
qk_bist_error
7
BIST has failed
qk_bist_ok
6
BIST has passed
qk_bist_active
5
BIST is in progress
qk_bist_running
4
BIST is in progress or finishing up (after qk_bist_enable = 0)
qk_bist_enable
0
Isolates QuiddiKey and runs BIST
qk_allow_bist
31
BIST is not allowed
QK_PSRPUF Score register; The PUF Score register shows the value of the PUF Score that was obtained during the last Test PUF, Enroll, Start or Reconstruct operation.
Address
0x448342DC
Reset
0x0000000F
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
qk_puf_score
3:0
PUF score obtained during the last Test PUF, Enroll, Start or Reconstruct operation
QK_HW_RUC0Module Restrict User Context 0 register; The Module Restrict User Context 0 register shows the values of the qk_restrict_user_context_0 signal on the signal interface.
Address
0x448342E0
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
qk_restrict_user_context_0
31:0
For each bit in the User_Context_0 field: 0: This bit can be used 1: This bit cannot be used
QK_HW_RUC1Module Restrict User Context 1 register; The Module Restrict User Context 1 register shows the values of the qk_restrict_user_context_1 signal on the signal interface.
Address
0x448342E4
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
qk_restrict_user_context_1
31:0
For each bit in the User_Context_1 field: 0: This bit can be used 1: This bit cannot be used
QK_HW_SETTINGSModule Settings register; The Module Settings register shows the values of the module settings on the signal interface.
Address
0x448342F0
Reset
0x00000000
Access
read only
Size
32-bit
12 fields
Field
Bits
What it does
qk_disable_test_memory
30
0: Test Memory operations are enabled 1: Test Memory operations are disabled
qk_skip_memory_test
29
0: Includes memory test during initialization 1: Skips memory test during initialization
qk_disable_generate_random
15
0: Generate Random operations are enabled 1: Generate Random operations are disabled
qk_disable_wrap
9
0: Wrap operations are enabled 1: Wrap operations are disabled
qk_disable_wrap_generated_random
8
0: Wrap Generated Random operations are enabled 1: Wrap Generated Random operations are disabled
qk_disable_unwrap
7
0: Unwrap operations are enabled 1: Unwrap operations are disabled
qk_disable_get_key
6
0: Get Key operations are enabled 1: Get Key operations are disabled
qk_disable_stop
5
0: Stop operations are enabled 1: Stop operations are disabled
qk_disable_reconstruct
3
0: Reconstruct operations are enabled 1: Reconstruct operations are disabled
qk_disable_start
2
0: Start operations are enabled 1: Start operations are disabled
qk_disable_enroll
1
0: Enroll operations are enabled 1: Enroll operations are disabled
qk_disable_test_puf
31
0: Test PUF operations are enabled 1: Test PUF operations are disabled
QK_HW_INFOModule Information register; The Module Information register indicates which configuration of QuiddiKey is used for this module and which options it includes.
Address
0x448342F4
Reset
0x21400000
Access
read only
Size
32-bit
5 fields
Field
Bits
What it does
qk_config_wrap
24
1: Wrap is included 0: Wrap is not included
Reserved
23
Safe: 1 Plus: 0
qk_config_bist
22
1: BIST is included 0: BIST is not included
qk_config_sp_800_90
21
1: SP 800-90 option is included 0: SP 800-90 option is not included
qk_config_type
31:28
QuiddiKey configuration
1
2
QK_HW_IDModule Identifier register; The Module Identifier register provides the identifier of the QuiddiKey Engine netlist.
Address
0x448342F8
Reset
0x20120702
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
qk_hw_id
31:0
Module identifier
QK_HW_VERModule Version register; The Module Version register provides the version of this module: major.minor.patch.
BETA