The 32 registers of DSU (Polaris Device Services Unit Macro DOS), from 0x44000000, with their reset value and every field. The PIC32CM5112SG00100 has 3618 registers in 68 peripherals, one page each.
DSU Polaris Device Services Unit Macro DOS
CTRLAControl A REGISTER
Address
0x44000000
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
PRIV
2
Privileged Access Only for APB Interface
0 Internal Address Space registers accessible in privileged and unprivileged modes. Test functions generate unprivileged requests.
1 Internal Address Space registers only accessible in privileged mode. Test functions generate privileged requests.
CTRLBControl B REGISTER
Address
0x44000004
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
DCCDMALVL1
1
DMA Trigger n Level
0 Trigger n rises when DCCn is read and falls when it is written
1 Trigger n rises when DCCn is written and falls when it is read
DCCDMALVL0
0
DMA Trigger n Level
0 Trigger n rises when DCCn is read and falls when it is written
1 Trigger n rises when DCCn is written and falls when it is read
MISC
31:8
Device Specific Configuration Register
CTRLCControl C REGISTER
Address
0x44000100
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DBGRW0
0
CPUn Debug R/W
0 Allow debugger accesses through CPUn to carry the debug attribute (i.e debugger reads are non-destructive).
1 Debugger accesses through CPUn do not carry the debug attribute (i.e debugger reads are destructive).
STATUSAStatus A REGISTER
Address
0x44000104
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
BREXT0
16
BootRom 0 Phase Extension Status
0 Boot ROM Phase Extension released for CPUx.
1 Boot ROM Phase Extension for CPUx. Set on Cold-Plugging detection.
CRSTEXT0
8
CPUx Reset Extension Status
0 CPUx released from reset extension.
1 CPUx held in reset extension. Set on Cold-Plugging detection.
ROMCRC
7:6
Boot ROM CRC Self-Check Status
0 CRC is in progress
1 CRC completed but failed indicating possible issue with the ROM content. System held in lockup state.
2 CRC completed and passed
3 CRC never executed because user disabled CRC check through fuse settings.
PERR
3
Protection Error Status
0 No protection error detected
1 Invalid command written to TCTRL.CMD, partial write to the upper or lower bytes of TCTRL.CMD, or invalid key written to SAFEDOOR.
BERR
2
Bus Error Status
0 No bus error detected
1 Bus error incurred while performing the DSU command.
DONE
0
Done Status
0 DSU is executing a command or idle.
1 TCTRL.CMD command completed
STATUSBStatus B REGISTER
Address
0x44000108
Reset
0x00000000
Access
read only
Size
32-bit
6 fields
Field
Bits
What it does
HPS
10
Hot-Plugging Status
0 Hot-Plugging inactive
1 Hot-Plugging active
DBGPRES
8
Debugger Present Status
0 No debugger detected
1 Debugger probe detected
DCCD1
3
Debug Communication Channel 1 Dirty
0 DCCDx.DATA register was read from.
1 DCCDx.DATA register was written to.
DCCD0
2
Debug Communication Channel 0 Dirty
0 DCCDx.DATA register was read from.
1 DCCDx.DATA register was written to.
BCCD1
1
Boot ROM Communication Channel 1 Dirty
0 BCCDx.DATA register was read from.
1 BCCDx.DATA register was written to.
BCCD0
0
Boot ROM Communication Channel 0 Dirty
0 BCCDx.DATA register was read from.
1 BCCDx.DATA register was written to.
BCC0Boot ROM Channel n REGISTER
Address
0x44000110
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DATA
31:0
Data
BCC1Boot ROM Channel n REGISTER
Address
0x44000114
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DATA
31:0
Data
DCC0Debug Communication Channel n REGISTER
Address
0x44000118
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DATA
31:0
Data
DCC1Debug Communication Channel n REGISTER
Address
0x4400011C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
DATA
31:0
Data
DIDDevice Identification Register
Address
0x44000120
Reset
0x0AC08053
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
PNMID
27:20
Part Number Mask ID
PNDID
19:12
Part Number Device ID
MANID
11:1
JEDEC Manufacture ID
FV
0
Fixed Value of 1
VER
31:28
Version Code
DALDebugger Access Level REGISTER
Address
0x44000124
Reset
0x00000000
Access
read only
Size
32-bit
4 fields
Field
Bits
What it does
CPU3
7:6
CPU n Debugger Access Level
0 Debugger access is disabled
1 Debugger can access only non-secure regions
2 Debugger has full access to debug CPUn
3 Unimplemented CPU
CPU2
5:4
CPU n Debugger Access Level
0 Debugger access is disabled
1 Debugger can access only non-secure regions
2 Debugger has full access to debug CPUn
3 Unimplemented CPU
CPU1
3:2
CPU n Debugger Access Level
0 Debugger access is disabled
1 Debugger can access only non-secure regions
2 Debugger has full access to debug CPUn
3 Unimplemented CPU
CPU0
1:0
CPU 0 Debugger Access Level
0 Debugger targeting CPU0 domain can only access the DSU external address space otherwise debugger access is disabled
1 Debugger can access only non-secure regions
2 Debugger can access secure and non-secure regions
ENTRY0CoreSight ROM Table Entry N Register
Address
0x44001000
Reset
0x9C0FE002
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
FMT
1
CoreSight Rom Table Format
0 8-bit format
1 32-bit format
EPRES
0
CoreSight Entry Present
0 Entry not present
1 Entry present
ADDOFF
31:12
CoreSight ROM Table Address Offset
ENTRY1CoreSight ROM Table Entry N Register
Address
0x44001004
Reset
0xBBFFF002
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
FMT
1
CoreSight Rom Table Format
0 8-bit format
1 32-bit format
EPRES
0
CoreSight Entry Present
0 Entry not present
1 Entry present
ADDOFF
31:12
CoreSight ROM Table Address Offset
ENTRY2CoreSight ROM Table Entry N Register
Address
0x44001008
Reset
0xBBFFF002
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
FMT
1
CoreSight Rom Table Format
0 8-bit format
1 32-bit format
EPRES
0
CoreSight Entry Present
0 Entry not present
1 Entry present
ADDOFF
31:12
CoreSight ROM Table Address Offset
ENTRY3CoreSight ROM Table Entry N Register
Address
0x4400100C
Reset
0xBBFFF002
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
FMT
1
CoreSight Rom Table Format
0 8-bit format
1 32-bit format
EPRES
0
CoreSight Entry Present
0 Entry not present
1 Entry present
ADDOFF
31:12
CoreSight ROM Table Address Offset
ENTRY4CoreSight ROM Table Entry 4 Register
Address
0x44001010
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
FMT
1
CoreSight Rom Table Format
0 8-bit format
1 32-bit format
EPRES
0
CoreSight Entry Present
0 Entry not present
1 Entry present
ADDOFF
31:12
CoreSight ROM Table Address Offset
ENTRY5CoreSight ROM Table Entry 5 Register
Address
0x44001014
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
FMT
1
CoreSight Rom Table Format
0 8-bit format
1 32-bit format
EPRES
0
CoreSight Entry Present
0 Entry not present
1 Entry present
ADDOFF
31:12
CoreSight ROM Table Address Offset
ENTRY6CoreSight ROM Table Entry 6 Register
Address
0x44001018
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
FMT
1
CoreSight Rom Table Format
0 8-bit format
1 32-bit format
EPRES
0
CoreSight Entry Present
0 Entry not present
1 Entry present
ADDOFF
31:12
CoreSight ROM Table Address Offset
ENTRY7CoreSight ROM Table Entry 7 Register
Address
0x4400101C
Reset
0x00000000
Access
read only
Size
32-bit
3 fields
Field
Bits
What it does
FMT
1
CoreSight Rom Table Format
0 8-bit format
1 32-bit format
EPRES
0
CoreSight Entry Present
0 Entry not present
1 Entry present
ADDOFF
31:12
CoreSight ROM Table Address Offset
MEMTYPECoreSight ROM Table Memory Type Register
Address
0x44001FCC
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
SYSMEM
0
CoreSight System Memory Present
0 System memory not present on bus. This is a dedicated debug bus.
BETA