CTRLAControl
- Address
0x44008000- Reset
0x00- Access
- read/write
- 7–
- 6–
- 5–
- 4–
- 3–
- 2–
- 1–
- 0SWRST
1 field
| Field | Bits | What it does |
|---|---|---|
| SWRST | 0 | Software Reset |
The 53 registers of GCLK (Generic Clock Generator), from 0x44008000, with their reset value and every field. The PIC32CM5112SG00100 has 3618 registers in 68 peripherals, one page each.
0x440080000x00| Field | Bits | What it does |
|---|---|---|
| SWRST | 0 | Software Reset |
0x440080040x00000000| Field | Bits | What it does |
|---|---|---|
| GENCTRL11 | 13 | Generic Clock Generator Control 11 Synchronization Busy bit |
| GENCTRL10 | 12 | Generic Clock Generator Control 10 Synchronization Busy bit |
| GENCTRL9 | 11 | Generic Clock Generator Control 9 Synchronization Busy bit |
| GENCTRL8 | 10 | Generic Clock Generator Control 8 Synchronization Busy bit |
| GENCTRL7 | 9 | Generic Clock Generator Control 7 Synchronization Busy bit |
| GENCTRL6 | 8 | Generic Clock Generator Control 6 Synchronization Busy bit |
| GENCTRL5 | 7 | Generic Clock Generator Control 5 Synchronization Busy bit |
| GENCTRL4 | 6 | Generic Clock Generator Control 4 Synchronization Busy bit |
| GENCTRL3 | 5 | Generic Clock Generator Control 3 Synchronization Busy bit |
| GENCTRL2 | 4 | Generic Clock Generator Control 2 Synchronization Busy bit |
| GENCTRL1 | 3 | Generic Clock Generator Control 1 Synchronization Busy bit |
| GENCTRL0 | 2 | Generic Clock Generator Control 0 Synchronization Busy bit |
| SWRST | 0 | Software Reset Synchronization Busy bit |
0x440080200x00000000| Field | Bits | What it does |
|---|---|---|
| RUNSTDBY | 13 | Run in Standby |
| DIVSEL | 12 | Divide Selection
|
| OE | 11 | Output Enable |
| OOV | 10 | Output Off Value |
| IDC | 9 | Improve Duty Cycle |
| GENEN | 8 | Generic Clock Generator Enable |
| SRC | 3:0 | Source Select
|
| DIV | 31:16 | Division Factor |
0x440080240x00000000| Field | Bits | What it does |
|---|---|---|
| RUNSTDBY | 13 | Run in Standby |
| DIVSEL | 12 | Divide Selection
|
| OE | 11 | Output Enable |
| OOV | 10 | Output Off Value |
| IDC | 9 | Improve Duty Cycle |
| GENEN | 8 | Generic Clock Generator Enable |
| SRC | 3:0 | Source Select
|
| DIV | 31:16 | Division Factor |
0x440080280x00000000| Field | Bits | What it does |
|---|---|---|
| RUNSTDBY | 13 | Run in Standby |
| DIVSEL | 12 | Divide Selection
|
| OE | 11 | Output Enable |
| OOV | 10 | Output Off Value |
| IDC | 9 | Improve Duty Cycle |
| GENEN | 8 | Generic Clock Generator Enable |
| SRC | 3:0 | Source Select
|
| DIV | 31:16 | Division Factor |
0x4400802C0x00000000| Field | Bits | What it does |
|---|---|---|
| RUNSTDBY | 13 | Run in Standby |
| DIVSEL | 12 | Divide Selection
|
| OE | 11 | Output Enable |
| OOV | 10 | Output Off Value |
| IDC | 9 | Improve Duty Cycle |
| GENEN | 8 | Generic Clock Generator Enable |
| SRC | 3:0 | Source Select
|
| DIV | 31:16 | Division Factor |
0x440080300x00000000| Field | Bits | What it does |
|---|---|---|
| RUNSTDBY | 13 | Run in Standby |
| DIVSEL | 12 | Divide Selection
|
| OE | 11 | Output Enable |
| OOV | 10 | Output Off Value |
| IDC | 9 | Improve Duty Cycle |
| GENEN | 8 | Generic Clock Generator Enable |
| SRC | 3:0 | Source Select
|
| DIV | 31:16 | Division Factor |
0x440080340x00000000| Field | Bits | What it does |
|---|---|---|
| RUNSTDBY | 13 | Run in Standby |
| DIVSEL | 12 | Divide Selection
|
| OE | 11 | Output Enable |
| OOV | 10 | Output Off Value |
| IDC | 9 | Improve Duty Cycle |
| GENEN | 8 | Generic Clock Generator Enable |
| SRC | 3:0 | Source Select
|
| DIV | 31:16 | Division Factor |
0x440080380x00000000| Field | Bits | What it does |
|---|---|---|
| RUNSTDBY | 13 | Run in Standby |
| DIVSEL | 12 | Divide Selection
|
| OE | 11 | Output Enable |
| OOV | 10 | Output Off Value |
| IDC | 9 | Improve Duty Cycle |
| GENEN | 8 | Generic Clock Generator Enable |
| SRC | 3:0 | Source Select
|
| DIV | 31:16 | Division Factor |
0x4400803C0x00000000| Field | Bits | What it does |
|---|---|---|
| RUNSTDBY | 13 | Run in Standby |
| DIVSEL | 12 | Divide Selection
|
| OE | 11 | Output Enable |
| OOV | 10 | Output Off Value |
| IDC | 9 | Improve Duty Cycle |
| GENEN | 8 | Generic Clock Generator Enable |
| SRC | 3:0 | Source Select
|
| DIV | 31:16 | Division Factor |
0x440080400x00000000| Field | Bits | What it does |
|---|---|---|
| RUNSTDBY | 13 | Run in Standby |
| DIVSEL | 12 | Divide Selection
|
| OE | 11 | Output Enable |
| OOV | 10 | Output Off Value |
| IDC | 9 | Improve Duty Cycle |
| GENEN | 8 | Generic Clock Generator Enable |
| SRC | 3:0 | Source Select
|
| DIV | 31:16 | Division Factor |
0x440080440x00000000| Field | Bits | What it does |
|---|---|---|
| RUNSTDBY | 13 | Run in Standby |
| DIVSEL | 12 | Divide Selection
|
| OE | 11 | Output Enable |
| OOV | 10 | Output Off Value |
| IDC | 9 | Improve Duty Cycle |
| GENEN | 8 | Generic Clock Generator Enable |
| SRC | 3:0 | Source Select
|
| DIV | 31:16 | Division Factor |
0x440080480x00000000| Field | Bits | What it does |
|---|---|---|
| RUNSTDBY | 13 | Run in Standby |
| DIVSEL | 12 | Divide Selection
|
| OE | 11 | Output Enable |
| OOV | 10 | Output Off Value |
| IDC | 9 | Improve Duty Cycle |
| GENEN | 8 | Generic Clock Generator Enable |
| SRC | 3:0 | Source Select
|
| DIV | 31:16 | Division Factor |
0x4400804C0x00000000| Field | Bits | What it does |
|---|---|---|
| RUNSTDBY | 13 | Run in Standby |
| DIVSEL | 12 | Divide Selection
|
| OE | 11 | Output Enable |
| OOV | 10 | Output Off Value |
| IDC | 9 | Improve Duty Cycle |
| GENEN | 8 | Generic Clock Generator Enable |
| SRC | 3:0 | Source Select
|
| DIV | 31:16 | Division Factor |
0x440080800x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080840x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080880x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x4400808C0x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080900x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080940x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080980x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x4400809C0x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080A00x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080A40x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080A80x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080AC0x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080B00x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080B40x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080B80x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080BC0x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080C00x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080C40x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080C80x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080CC0x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080D00x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080D40x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080D80x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080DC0x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080E00x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080E40x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080E80x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080EC0x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080F00x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080F40x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080F80x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440080FC0x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440081000x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440081040x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440081080x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x4400810C0x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440081100x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440081140x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|
0x440081180x00000000| Field | Bits | What it does |
|---|---|---|
| WRTLOCK | 7 | Write Lock |
| CHEN | 6 | Channel Enable |
| GEN | 3:0 | Generic Clock Generator
|