The 57 registers of HSM (Cryptographic Acceleration Module Lite), from 0x4F000000, with their reset value and every field. The PIC32CM5112SG00100 has 3618 registers in 68 peripherals, one page each.
HSM Cryptographic Acceleration Module Lite
CTRLAControl Register A
Address
0x4F000000
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
RUNSTDBY
6
Run In Standby bit
0 HSM clock is disabled in Standby Sleep mode, clock requests are de-asserted after any pending bus transactions or requests are completed.
1 If enabled, the HSM clock remains requested in Standby Sleep mode.
PRIV
2
Privileged Access Only - This bit affects all Wrapper and EIP registers.
0 HSM registers accessible in privileged and unprivileged modes. Master Requests are NOT privileged
1 HSM registers only accessible in privileged mode. Master Requests are also privileged.
ENABLE
1
Macro/Clock Enable bit
0 HSM clock is not requested and macros is disabled.
1 HSM clock is requested and macro is enabled.
SWRST
0
Software Reset1 = Reset registers and internal state0 = No effect
STATUSASTATUS Register A
Address
0x4F000038
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
OTPLOCK
0
OTP Lock bit
1 OTP lock bit set. Device not in IC manufacturing.
SYNCBUSYSYNCBUSY Register
Address
0x4F00005C
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
ENABLE
1
Macro Enable Synchronization Busy
0 ENABLE synchronization is NOT busy.
1 ENABLE synchronization is busy.
SWRST
0
Software Reset Synchronization Busy1 = SWRST synchronization is busy0 = SWRST synchronization is NOT busy
DMA_Registers__FETCH_ADDR_LSB
Address
0x4F010000
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
FETCH_ADDR_LSB
31:0
DMA_Registers__FETCH_ADDR_MSB
Address
0x4F010004
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
FETCH_ADDR_MSB
31:0
DMA_Registers__FETCH_LEN
Address
0x4F010008
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
FETCH_ZPADDING
30
FETCH_REALIGN
29
FETCH_CSTADDR
28
FETCH_LEN
27:0
DMA_Registers__FETCH_TAG
Address
0x4F01000C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
FETCH_TAG
31:0
DMA_Registers__PUSH_ADDR_LSB
Address
0x4F010010
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
PUSH_ADDR_LSB
31:0
DMA_Registers__PUSH_ADDR_MSB
Address
0x4F010014
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
PUSH_ADDR_MSB
31:0
DMA_Registers__PUSH_LEN
Address
0x4F010018
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
PUSH_DISCARD
30
PUSH_REALIGN
29
PUSH_CSTADDR
28
PUSH_LEN
27:0
DMA_Registers__INT_EN
Address
0x4F01001C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
INT_EN
5:0
DMA_Registers__INT_ENSET
Address
0x4F010020
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
INT_ENSET
5:0
DMA_Registers__INT_ENCLR
Address
0x4F010024
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
INT_ENCLR
5:0
DMA_Registers__INT_STATRAW
Address
0x4F010028
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
INT_STATRAW
5:0
DMA_Registers__INT_STAT
Address
0x4F01002C
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
INT_STAT
5:0
DMA_Registers__INT_STATCLR
Address
0x4F010030
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
INT_STATCLR
5:0
DMA_Registers__CONFIG
Address
0x4F010034
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
SOFT_RST
4
PUSH_STOP
3
FETCH_STOP
2
PUSH_CTRL_INDIRECT
1
FETCH_CTRL_INDIRECT
0
DMA_Registers__START
Address
0x4F010038
Reset
0x00000000
Access
write only
Size
32-bit
2 fields
Field
Bits
What it does
START_PUSH
1
START_FETCH
0
DMA_Registers__STATUS
Address
0x4F01003C
Reset
0x00000000
Access
read only
Size
32-bit
6 fields
Field
Bits
What it does
SOFT_RST_BUSY
6
PUSH_WAITINGFIFO
5
FETCH_NOT_EMPTY
4
PUSH_BUSY
1
FETCH_BUSY
0
PUSH_NBDATA
31:16
Registers__INCL_IPS_HW_CFG
Address
0x4F010400
Reset
0x00000611
Access
read only
Size
32-bit
14 fields
Field
Bits
What it does
BA422_KASUMI_INCLUDED
13
Generic g_IncludeKasumi value. BA422-Kasumi IP included if set
BA423_SNOW3G_INCLUDED
12
Generic g_IncludeSnow3G value. BA423-Snow3G IP included if set
BA420_HP_CHACHAPOLY_INCLUDED
11
Generic g_IncludeHPChachaPoly value. BA420-HP-ChaChaPoly IP included if set
BA431_NDRNG_INCLUDED
10
Generic g_IncludeNDRNG value. BA431-NDRNG IP included if set
BA414EP_PKE_INCLUDED
9
Generic g_IncludePKE value. BA414EP-PKE IP included if set
BA419_SM4_INCLUDED
8
Generic g_IncludeSM4 value. BA419-SM4 IP included if set
BA421_ZUC_INCLUDED
7
Generic g_IncludeZUC value. BA421-ZUC IP included if set
BA418_SHA3_INCLUDED
6
Generic g_IncludeSHA3 value. BA418-SHA3 IP included if set
BA417_CHACHAPOLY_INCLUDED
5
Generic g_IncludeChachaPoly value. BA417-ChaChaPoly IP included if set
BA413_HASH_INCLUDED
4
Generic g_IncludeHASH value. BA413-HASH IP included if set
BA412_DES_INCLUDED
3
Generic g_IncludeDES value. BA412-3DES IP included if set
BA416_HP_AES_XTS_INCLUDED
2
Generic g_IncludeAESXTS value. BA416-HP-AES-XTS IP included if set
BA415_HP_AES_GCM_INCLUDED
1
Generic g_IncludeAESGCM value. BA415-HP-AES-GCM IP included if set
BA411_AES_INCLUDED
0
Generic g_IncludeAES value. BA411E-AES IP included if set
Enable write of the samples in the FIFO during start-up.
Nb128BitBlocks
19:16
Number of 128 bit blocks used in AES-CBCMAC post-processing. This value cannot be zero.
AIS31TestSel
15
Select input to the AIS31 test module: 0: Before conditioning, 1: After conditioning.
HealthTestSel
14
Select input to health test module: 0: Before conditioning, 1: After conditioning.
AIS31Bypass
13
Bypass AIS31 tests such that the results of the start-up and online tests do not affect the FSM state.
HealthTestBypass
12
Bypass NIST tests such that the results of the start-up and online test do not affect the FSM state.
ForceActiveROs
11
Force oscillators to run when FIFO is full.
IntEnAlm
10
Interrupt enable for AIS31 noise alarm.
IntEnPre
9
Interrupt enable for AIS31 preliminary noise alarm.
SoftRst
8
Software reset: 0: Normal mode, 1: The continuous test, the conditioning function and the FIFO are reset. This bit is not cleared automatically.
IntEnFull
7
Interrupt enable for FIFO full.
IntEnProp
5
Interrupt enable for Adaptive Proportion Test failure (1024-sample window).
IntEnRep
4
Interrupt enable for Repetition Count Test failure.
CondBypass
3
0: the conditioning function is used (normal mode), 1: the conditioning function is bypassed (to observe entropy source directly).
TestEn
2
Select input for conditioning function and continuous tests: 0: Noise source (normal mode), 1: Test data register (test mode).
LFSREn
1
Select between the NDRNG with asynchronous free running oscillators (when '0') and the Pseudo-Random generator with synchronous oscillators for simulation purpose (when '1').
When executing primitive arithmetic operations, this pointer defines the location where the modulus is located in memory (location 0x0 to 0xF).
OpPtrC
19:16
When executing primitive arithmetic operations, this pointer defines the location (0x0 to 0xF) where the result will be stored in memory.
OpPtrB
11:8
When executing primitive arithmetic operations, this pointer defines where operand B is located in memory (location 0x0 to 0xF).
OpPtrA
3:0
When executing primitive arithmetic operations, this pointer defines where operand A is located in memory (location 0x0 to 0xF).
PK_Registers__CommandCommand register.
Address
0x4F012004
Reset
0x0000000F
Access
read/write
Size
32-bit
12 fields
Field
Bits
What it does
FlagB
30
See operation description.
FlagA
29
See operation description.
SwapBytes
28
Swap the bytes on AHB interface: '0': Native format (little endian) '1': Byte swapped (big endian) See also section 4.2.1. This bit must be programmed before writing/reading any data in data memory.
Edwards
26
Enable Edwards curve (see operation description).
RandProj
25
Enable randomization of projective coordinates (counter-measure).
RandKE
24
Enable randomization of exponent/scalar (counter-measure).
SelCurve
22:20
Enable accelerator for specific curve modulus: 0x0: No acceleration (default) 0x1: P256 0x2: P384 0x3: P521 0x4: P192 0x5: Curve25519 0x6: Ed25519 This field has no effect when the optional acceleration hardware is not included.
RandMod
19
Enable randomization of modulus (counter-measure).
OpBytesM1
17:8
This field defines the size (= number of bytes minus one) of the operands for the current operation. Possible values are limited by the maximum supported operand size. Examples: - 0x014 -> ECC on curve K-163 - 0x01F -> ECC on curve P-256 - 0x02F -> ECC on curve P-384 - 0x033 -> ECC on curve K-409 -
FieldF
7
'0': Field is GF(p) '1': Field is GF(2**m)
OpeAddr
6:0
This field defines the operation to be performed. See documentation for more details.
CalcR2
31
This bit indicates if the IP has to calculate R**2 mod N for the next operation. This bit must be set to '1' when a new prime number has been programmed. This bit is used for primitive operations and ignored for the other operations. '0': don't recalculate R**2 mod N '1': re-calculate R**2 mod N
PK_Registers__ControlCommand register.
Address
0x4F012008
Reset
0x00000000
Access
write only
Size
32-bit
2 fields
Field
Bits
What it does
ClearIRQ
1
Writing a '1' clears the IRQ output.
Start
0
Writing a '1' starts the processing.
PK_Registers__StatusStatus register.
Address
0x4F01200C
Reset
0x00000000
Access
read only
Size
32-bit
4 fields
Field
Bits
What it does
FailPtr
28:24
These bits indicate which data location generated the error flag. They are not available for all error flags.
IntrptStatus
17
This bit reflects the IRQ output value. It is set when the operation is finished. It is cleared when the CPU writes the bit 1 of Control Register.
PK_Busy
16
This bit reflects the BUSY output value. It is set when the operation starts and it is cleared when the operation is finished.
ErrorFlags
15:4
These bits indicate an error condition. They are updated at the end of the operation. They are cleared when starting a new operation. See documentation for more details.
State of DisableClrMem input (high when automatic clear of the RAM after reset is disabled).
DisableSM
29
State of DisableSMx input (high when SM2/SM9 operations are disabled).
AHBMaster
25
'0': Memory access through AHB Slave and internally in the PKE. '1': Memory access through AHB Master, outside the PKE.
X25519
24
Support Curve25519/Ed25519 acceleration.
P192
23
Support ECC P192 acceleration.
P521
22
Support ECC P521 acceleration.
P384
21
Support ECC P384 acceleration.
P256
20
Support ECC P256 acceleration.
ECC
18
Support RAM error correction.
BinaryField
17
Support binary field.
PrimeField
16
Support prime field.
NbMult
15:12
Number of multipliers: 0x0: 1 multiplier 0x1: 4 multipliers 0x2: 16 multipliers 0x4: 64 multipliers 0x8: 256 multipliers
MaxOpSize
11:0
Maximum operand size (number of bytes).
DisableCM
31
State of DisableCM input (high when counter-measures are disabled).
PK_Registers__OpSizeOperand size register.
Address
0x4F01201C
Reset
0x00001000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
OpSize
12:0
Operand size (number of bytes): 0x0100: 256 0x0209: 521 0x0800: 2048 0x0C00: 3072 0x1000: 4096 This register is used when the memory is accessed via AHB Master
BETA