The 15 registers of NVMCTRL (Non-Volatile Memory Controller), from 0x41004000, with their reset value and every field. The PIC32CM5164LE00048 has 1757 registers in 48 peripherals, one page each.
NVMCTRL Non-Volatile Memory Controller
CTRLAControl A
Address
0x41004000
Reset
0x0000
Access
write only
Size
16-bit
2 fields
Field
Bits
What it does
CMDEX
15:8
Command Execution
165 Execution Key
CMD
6:0
Command
2 Erase Row - Erases the row addressed by the ADDR register.
4 Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register.
66 Sets the power reduction mode.
67 Clears the power reduction mode.
68 Page Buffer Clear - Clears the page buffer.
70 Invalidate all cache lines.
75 Set DAL=0
CTRLBControl B
Address
0x41004004
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
Field
Bits
What it does
CACHEDIS
18
Cache Disable
READMODE
17:16
NVMCTRL Read Mode
0 The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance.
1 Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time.
2 The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings.
FWUP
11
fast wake-up
SLEEPPRM
9:8
Power Reduction Mode during Sleep
0 NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access.
1 NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep.
3 Auto power reduction disabled.
RWS
4:1
NVM Read Wait States
CTRLCControl C
Address
0x41004008
Reset
0x01
Access
read/write
7–
6–
5–
4–
3–
2–
1–
0MANW
1 field
Field
Bits
What it does
MANW
0
Manual Write
EVCTRLEvent Control
Address
0x4100400A
Reset
0x00
Access
read/write
7–
6–
5–
4–
3–
2–
1AUTOWINV
0AUTOWEI
2 fields
Field
Bits
What it does
AUTOWINV
1
Auto Write Event Polarity Inverted
AUTOWEI
0
Auto Write Event Enable
INTENCLRInterrupt Enable Clear
Address
0x4100400C
Reset
0x00
Access
read/write
7–
6–
5–
4KEYE
3NVME
2LOCKE
1PROGE
0DONE
5 fields
Field
Bits
What it does
KEYE
4
Key Write Error Interrupt Clear
NVME
3
NVM Error Interrupt Clear
LOCKE
2
Lock Error Status Interrupt Clear
PROGE
1
Programming Error Status Interrupt Clear
DONE
0
NVM Done Interrupt Clear
INTENSETInterrupt Enable Set
Address
0x41004010
Reset
0x00
Access
read/write
7–
6–
5–
4KEYE
3NVME
2LOCKE
1PROGE
0DONE
5 fields
Field
Bits
What it does
KEYE
4
Key Write Error Interrupt Enable
NVME
3
NVM Error Interrupt Enable
LOCKE
2
Lock Error Status Interrupt Enable
PROGE
1
Programming Error Status Interrupt Enable
DONE
0
NVM Done Interrupt Enable
INTFLAGInterrupt Flag Status and Clear
Address
0x41004014
Reset
0x00
Access
read/write
7–
6–
5–
4KEYE
3NVME
2LOCKE
1PROGE
0DONE
5 fields
Field
Bits
What it does
KEYE
4
KEY Write Error
NVME
3
NVM Error
LOCKE
2
Lock Error Status
PROGE
1
Programming Error Status
DONE
0
NVM Done
STATUSStatus
Address
0x41004018
Reset
0x0000
Access
read only
Size
16-bit
4 fields
Field
Bits
What it does
DALFUSE
4:3
Debug Access Level Fuse
0 Access to very limited features
2 Access to all memory. Can debug secure and non-secure CPU code
BETA