The 28 registers of TCC3 (Timer Counter for Control Applications), from 0x42003400, with their reset value and every field. The PIC32CM5164LS60048 has 2318 registers in 56 peripherals, one page each.
TCC3 Timer Counter for Control Applications
CTRLAControl A
Address
0x42003400
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
Field
Bits
What it does
CPTEN3
27
Capture Channel 3 Enable
CPTEN2
26
Capture Channel 2 Enable
CPTEN1
25
Capture Channel 1 Enable
CPTEN0
24
Capture Channel 0 Enable
DMAOS
23
DMA One-shot Trigger Mode
FCYCLE
16
Full Cycle
MSYNC
15
Master Synchronization (only for TCC Slave Instance)
ALOCK
14
Auto Lock
PRESCSYNC
13:12
Prescaler and Counter Synchronization Selection
0 Reload or reset counter on next GCLK
1 Reload or reset counter on next prescaler clock
2 Reload or reset counter on next GCLK and reset prescaler counter
RUNSTDBY
11
Run in Standby
PRESCALER
10:8
Prescaler
0 No division
1 Divide by 2
2 Divide by 4
3 Divide by 8
4 Divide by 16
5 Divide by 64
6 Divide by 256
7 Divide by 1024
RESOLUTION
6:5
Enhanced Resolution
0 Dithering is disabled
1 Dithering is done every 16 PWM frames
2 Dithering is done every 32 PWM frames
3 Dithering is done every 64 PWM frames
ENABLE
1
Enable
SWRST
0
Software Reset
CTRLBCLRControl B Clear
Address
0x42003404
Reset
0x00
Access
read/write
7CMD2
6CMD1
5CMD0
4IDXCMD1
3IDXCMD0
2ONESHOT
1LUPD
0DIR
5 fields
Field
Bits
What it does
CMD
7:5
TCC Command
0 No action
1 Clear start, restart or retrigger
2 Force stop
3 Force update or double buffered registers
4 Force COUNT read synchronization
5 One-shot DMA trigger
IDXCMD
4:3
Ramp Index Command
0 Command disabled: Index toggles between cycles A and B
1 Set index: cycle B will be forced in the next cycle
2 Clear index: cycle A will be forced in the next cycle
3 Hold index: the next cycle will be the same as the current cycle
ONESHOT
2
One-Shot
LUPD
1
Lock Update
DIR
0
Counter Direction
CTRLBSETControl B Set
Address
0x42003405
Reset
0x00
Access
read/write
7CMD2
6CMD1
5CMD0
4IDXCMD1
3IDXCMD0
2ONESHOT
1LUPD
0DIR
5 fields
Field
Bits
What it does
CMD
7:5
TCC Command
0 No action
1 Clear start, restart or retrigger
2 Force stop
3 Force update or double buffered registers
4 Force COUNT read synchronization
5 One-shot DMA trigger
IDXCMD
4:3
Ramp Index Command
0 Command disabled: Index toggles between cycles A and B
1 Set index: cycle B will be forced in the next cycle
2 Clear index: cycle A will be forced in the next cycle
3 Hold index: the next cycle will be the same as the current cycle
ONESHOT
2
One-Shot
LUPD
1
Lock Update
DIR
0
Counter Direction
SYNCBUSYSynchronization Busy
Address
0x42003408
Reset
0x00000000
Access
read only
Size
32-bit
12 fields
Field
Bits
What it does
CC3
11
Compare Channel 3 Busy
CC2
10
Compare Channel 2 Busy
CC1
9
Compare Channel 1 Busy
CC0
8
Compare Channel 0 Busy
PER
7
Period Busy
WAVE
6
Wave Busy
PATT
5
Pattern Busy
COUNT
4
Count Busy
STATUS
3
Status Busy
CTRLB
2
Ctrlb Busy
ENABLE
1
Enable Busy
SWRST
0
Swrst Busy
FCTRLARecoverable Fault A Configuration
Address
0x4200340C
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FILTERVAL
27:24
Fault A Filter Value
BLANKVAL
23:16
Fault A Blanking Time
BLANKPRESC
15
Fault A Blanking Prescaler
CAPTURE
14:12
Fault A Capture Action
0 No capture
1 Capture on fault
2 Minimum capture
3 Maximum capture
4 Minimum local detection
5 Maximum local detection
6 Minimum and maximum local detection
7 Capture with ramp index as MSB value
CHSEL
11:10
Fault A Capture Channel
0 Capture value stored in channel 0
1 Capture value stored in channel 1
2 Capture value stored in channel 2
3 Capture value stored in channel 3
HALT
9:8
Fault A Halt Mode
0 Halt action disabled
1 Hardware halt action
2 Software halt action
3 Non-recoverable fault
RESTART
7
Fault A Restart
BLANK
6:5
Fault A Blanking Mode
0 Blanking applied from start of the ramp
1 Blanking applied from rising edge of the output waveform
2 Blanking applied from falling edge of the output waveform
3 Blanking applied from each toggle of the output waveform
QUAL
4
Fault A Qualification
KEEP
3
Fault A Keeper
SRC
1:0
Fault A Source
0 Fault input disabled
1 MCEx (x=0,1) event input
2 Inverted MCEx (x=0,1) event input
3 Alternate fault (A or B) state at the end of the previous period
FCTRLBRecoverable Fault B Configuration
Address
0x42003410
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
FILTERVAL
27:24
Fault B Filter Value
BLANKVAL
23:16
Fault B Blanking Time
BLANKPRESC
15
Fault B Blanking Prescaler
CAPTURE
14:12
Fault B Capture Action
0 No capture
1 Capture on fault
2 Minimum capture
3 Maximum capture
4 Minimum local detection
5 Maximum local detection
6 Minimum and maximum local detection
7 Capture with ramp index as MSB value
CHSEL
11:10
Fault B Capture Channel
0 Capture value stored in channel 0
1 Capture value stored in channel 1
2 Capture value stored in channel 2
3 Capture value stored in channel 3
HALT
9:8
Fault B Halt Mode
0 Halt action disabled
1 Hardware halt action
2 Software halt action
3 Non-recoverable fault
RESTART
7
Fault B Restart
BLANK
6:5
Fault B Blanking Mode
0 Blanking applied from start of the ramp
1 Blanking applied from rising edge of the output waveform
2 Blanking applied from falling edge of the output waveform
3 Blanking applied from each toggle of the output waveform
QUAL
4
Fault B Qualification
KEEP
3
Fault B Keeper
SRC
1:0
Fault B Source
0 Fault input disabled
1 MCEx (x=0,1) event input
2 Inverted MCEx (x=0,1) event input
3 Alternate fault (A or B) state at the end of the previous period
WEXCTRLWaveform Extension Configuration
Address
0x42003414
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
DTLS
23:16
Dead-time Low Side Outputs Value
DTIEN3
11
Dead-time Insertion Generator 3 Enable
DTIEN2
10
Dead-time Insertion Generator 2 Enable
DTIEN1
9
Dead-time Insertion Generator 1 Enable
DTIEN0
8
Dead-time Insertion Generator 0 Enable
OTMX
1:0
Output Matrix
DTHS
31:24
Dead-time High Side Outputs Value
DRVCTRLDriver Control
Address
0x42003418
Reset
0x00000000
Access
read/write
Size
32-bit
26 fields
Field
Bits
What it does
FILTERVAL0
27:24
Non-Recoverable Fault Input 0 Filter Value
INVEN7
23
Output Waveform 7 Inversion
INVEN6
22
Output Waveform 6 Inversion
INVEN5
21
Output Waveform 5 Inversion
INVEN4
20
Output Waveform 4 Inversion
INVEN3
19
Output Waveform 3 Inversion
INVEN2
18
Output Waveform 2 Inversion
INVEN1
17
Output Waveform 1 Inversion
INVEN0
16
Output Waveform 0 Inversion
NRV7
15
Non-Recoverable State 7 Output Value
NRV6
14
Non-Recoverable State 6 Output Value
NRV5
13
Non-Recoverable State 5 Output Value
NRV4
12
Non-Recoverable State 4 Output Value
NRV3
11
Non-Recoverable State 3 Output Value
NRV2
10
Non-Recoverable State 2 Output Value
NRV1
9
Non-Recoverable State 1 Output Value
NRV0
8
Non-Recoverable State 0 Output Value
NRE7
7
Non-Recoverable State 7 Output Enable
NRE6
6
Non-Recoverable State 6 Output Enable
NRE5
5
Non-Recoverable State 5 Output Enable
NRE4
4
Non-Recoverable State 4 Output Enable
NRE3
3
Non-Recoverable State 3 Output Enable
NRE2
2
Non-Recoverable State 2 Output Enable
NRE1
1
Non-Recoverable State 1 Output Enable
NRE0
0
Non-Recoverable State 0 Output Enable
FILTERVAL1
31:28
Non-Recoverable Fault Input 1 Filter Value
DBGCTRLDebug Control
Address
0x4200341E
Reset
0x00
Access
read/write
7–
6–
5–
4–
3–
2FDDBD
1–
0DBGRUN
2 fields
Field
Bits
What it does
FDDBD
2
Fault Detection on Debug Break Detection
DBGRUN
0
Debug Running Mode
EVCTRLEvent Control
Address
0x42003420
Reset
0x00000000
Access
read/write
Size
32-bit
18 fields
Field
Bits
What it does
MCEO3
27
Match or Capture Channel 3 Event Output Enable
MCEO2
26
Match or Capture Channel 2 Event Output Enable
MCEO1
25
Match or Capture Channel 1 Event Output Enable
MCEO0
24
Match or Capture Channel 0 Event Output Enable
MCEI3
19
Match or Capture Channel 3 Event Input Enable
MCEI2
18
Match or Capture Channel 2 Event Input Enable
MCEI1
17
Match or Capture Channel 1 Event Input Enable
MCEI0
16
Match or Capture Channel 0 Event Input Enable
TCEI1
15
Timer/counter Event 1 Input Enable
TCEI0
14
Timer/counter Event 0 Input Enable
TCINV1
13
Inverted Event 1 Input Enable
TCINV0
12
Inverted Event 0 Input Enable
CNTEO
10
Timer/counter Output Event Enable
TRGEO
9
Retrigger Output Event Enable
OVFEO
8
Overflow/Underflow Output Event Enable
CNTSEL
7:6
Timer/counter Output Event Mode
0 An interrupt/event is generated when a new counter cycle starts
1 An interrupt/event is generated when a counter cycle ends
3 An interrupt/event is generated when a new counter cycle starts or a counter cycle ends
EVACT1
5:3
Timer/counter Input Event1 Action
0 Event action disabled
1 Re-trigger counter on event
2 Direction control
3 Stop counter on event
4 Decrement counter on event
6 Period capture value in CC1 register, pulse width capture value in CC0 register