PIC32CM6408JH00032 HMATRIXHS registers

The 57 registers of HMATRIXHS (HSB Matrix), from 0x4100A000, with their reset value and every field. The PIC32CM6408JH00032 has 917 registers in 39 peripherals, one page each.

HMATRIXHS HSB Matrix

MCFG0Master Configuration

Address
0x4100A000
Reset
0x00000002
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Infinite Length
  • 1 Single Access
  • 2 Four Beat Burst
  • 3 Eight Beat Burst
  • 4 Sixteen Beat Burst

MCFG1Master Configuration

Address
0x4100A004
Reset
0x00000002
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Infinite Length
  • 1 Single Access
  • 2 Four Beat Burst
  • 3 Eight Beat Burst
  • 4 Sixteen Beat Burst

MCFG2Master Configuration

Address
0x4100A008
Reset
0x00000002
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Infinite Length
  • 1 Single Access
  • 2 Four Beat Burst
  • 3 Eight Beat Burst
  • 4 Sixteen Beat Burst

MCFG3Master Configuration

Address
0x4100A00C
Reset
0x00000002
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Infinite Length
  • 1 Single Access
  • 2 Four Beat Burst
  • 3 Eight Beat Burst
  • 4 Sixteen Beat Burst

MCFG4Master Configuration

Address
0x4100A010
Reset
0x00000002
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Infinite Length
  • 1 Single Access
  • 2 Four Beat Burst
  • 3 Eight Beat Burst
  • 4 Sixteen Beat Burst

MCFG5Master Configuration

Address
0x4100A014
Reset
0x00000002
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Infinite Length
  • 1 Single Access
  • 2 Four Beat Burst
  • 3 Eight Beat Burst
  • 4 Sixteen Beat Burst

MCFG6Master Configuration

Address
0x4100A018
Reset
0x00000002
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Infinite Length
  • 1 Single Access
  • 2 Four Beat Burst
  • 3 Eight Beat Burst
  • 4 Sixteen Beat Burst

MCFG7Master Configuration

Address
0x4100A01C
Reset
0x00000002
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Infinite Length
  • 1 Single Access
  • 2 Four Beat Burst
  • 3 Eight Beat Burst
  • 4 Sixteen Beat Burst

MCFG8Master Configuration

Address
0x4100A020
Reset
0x00000002
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Infinite Length
  • 1 Single Access
  • 2 Four Beat Burst
  • 3 Eight Beat Burst
  • 4 Sixteen Beat Burst

MCFG9Master Configuration

Address
0x4100A024
Reset
0x00000002
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Infinite Length
  • 1 Single Access
  • 2 Four Beat Burst
  • 3 Eight Beat Burst
  • 4 Sixteen Beat Burst

MCFG10Master Configuration

Address
0x4100A028
Reset
0x00000002
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Infinite Length
  • 1 Single Access
  • 2 Four Beat Burst
  • 3 Eight Beat Burst
  • 4 Sixteen Beat Burst

MCFG11Master Configuration

Address
0x4100A02C
Reset
0x00000002
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Infinite Length
  • 1 Single Access
  • 2 Four Beat Burst
  • 3 Eight Beat Burst
  • 4 Sixteen Beat Burst

MCFG12Master Configuration

Address
0x4100A030
Reset
0x00000002
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Infinite Length
  • 1 Single Access
  • 2 Four Beat Burst
  • 3 Eight Beat Burst
  • 4 Sixteen Beat Burst

MCFG13Master Configuration

Address
0x4100A034
Reset
0x00000002
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Infinite Length
  • 1 Single Access
  • 2 Four Beat Burst
  • 3 Eight Beat Burst
  • 4 Sixteen Beat Burst

MCFG14Master Configuration

Address
0x4100A038
Reset
0x00000002
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Infinite Length
  • 1 Single Access
  • 2 Four Beat Burst
  • 3 Eight Beat Burst
  • 4 Sixteen Beat Burst

MCFG15Master Configuration

Address
0x4100A03C
Reset
0x00000002
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ULBT2:0Undefined Length Burst Type
  • 0 Infinite Length
  • 1 Single Access
  • 2 Four Beat Burst
  • 3 Eight Beat Burst
  • 4 Sixteen Beat Burst

SCFG0Slave Configuration

Address
0x4100A040
Reset
0x00000010
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ARBT24Arbitration Type
  • 0 Round-Robin Arbitration
  • 1 Fixed Priority Arbitration
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE7:0Maximum Number of Allowed Cycles for a Burst

SCFG1Slave Configuration

Address
0x4100A044
Reset
0x00000010
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ARBT24Arbitration Type
  • 0 Round-Robin Arbitration
  • 1 Fixed Priority Arbitration
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE7:0Maximum Number of Allowed Cycles for a Burst

SCFG2Slave Configuration

Address
0x4100A048
Reset
0x00000010
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ARBT24Arbitration Type
  • 0 Round-Robin Arbitration
  • 1 Fixed Priority Arbitration
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE7:0Maximum Number of Allowed Cycles for a Burst

SCFG3Slave Configuration

Address
0x4100A04C
Reset
0x00000010
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ARBT24Arbitration Type
  • 0 Round-Robin Arbitration
  • 1 Fixed Priority Arbitration
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE7:0Maximum Number of Allowed Cycles for a Burst

SCFG4Slave Configuration

Address
0x4100A050
Reset
0x00000010
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ARBT24Arbitration Type
  • 0 Round-Robin Arbitration
  • 1 Fixed Priority Arbitration
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE7:0Maximum Number of Allowed Cycles for a Burst

SCFG5Slave Configuration

Address
0x4100A054
Reset
0x00000010
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ARBT24Arbitration Type
  • 0 Round-Robin Arbitration
  • 1 Fixed Priority Arbitration
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE7:0Maximum Number of Allowed Cycles for a Burst

SCFG6Slave Configuration

Address
0x4100A058
Reset
0x00000010
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ARBT24Arbitration Type
  • 0 Round-Robin Arbitration
  • 1 Fixed Priority Arbitration
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE7:0Maximum Number of Allowed Cycles for a Burst

SCFG7Slave Configuration

Address
0x4100A05C
Reset
0x00000010
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ARBT24Arbitration Type
  • 0 Round-Robin Arbitration
  • 1 Fixed Priority Arbitration
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE7:0Maximum Number of Allowed Cycles for a Burst

SCFG8Slave Configuration

Address
0x4100A060
Reset
0x00000010
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ARBT24Arbitration Type
  • 0 Round-Robin Arbitration
  • 1 Fixed Priority Arbitration
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE7:0Maximum Number of Allowed Cycles for a Burst

SCFG9Slave Configuration

Address
0x4100A064
Reset
0x00000010
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ARBT24Arbitration Type
  • 0 Round-Robin Arbitration
  • 1 Fixed Priority Arbitration
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE7:0Maximum Number of Allowed Cycles for a Burst

SCFG10Slave Configuration

Address
0x4100A068
Reset
0x00000010
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ARBT24Arbitration Type
  • 0 Round-Robin Arbitration
  • 1 Fixed Priority Arbitration
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE7:0Maximum Number of Allowed Cycles for a Burst

SCFG11Slave Configuration

Address
0x4100A06C
Reset
0x00000010
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ARBT24Arbitration Type
  • 0 Round-Robin Arbitration
  • 1 Fixed Priority Arbitration
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE7:0Maximum Number of Allowed Cycles for a Burst

SCFG12Slave Configuration

Address
0x4100A070
Reset
0x00000010
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ARBT24Arbitration Type
  • 0 Round-Robin Arbitration
  • 1 Fixed Priority Arbitration
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE7:0Maximum Number of Allowed Cycles for a Burst

SCFG13Slave Configuration

Address
0x4100A074
Reset
0x00000010
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ARBT24Arbitration Type
  • 0 Round-Robin Arbitration
  • 1 Fixed Priority Arbitration
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE7:0Maximum Number of Allowed Cycles for a Burst

SCFG14Slave Configuration

Address
0x4100A078
Reset
0x00000010
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ARBT24Arbitration Type
  • 0 Round-Robin Arbitration
  • 1 Fixed Priority Arbitration
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE7:0Maximum Number of Allowed Cycles for a Burst

SCFG15Slave Configuration

Address
0x4100A07C
Reset
0x00000010
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
ARBT24Arbitration Type
  • 0 Round-Robin Arbitration
  • 1 Fixed Priority Arbitration
FIXED_DEFMSTR21:18Fixed Index of Default Master
DEFMSTR_TYPE17:16Default Master Type
  • 0 No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This resusts in having a one cycle latency for the first transfer of a burst.
  • 1 Last Default Master At the end of current slave access, if no other master request is pending, the slave stay connected with the last master havingaccessed it.This resusts in not having the one cycle latency when the last master re-trying access on the slave.
  • 2 Fixed Default Master At the end of current slave access, if no other master request is pending, the slave connects with fixed master which numberis in FIXED_DEFMSTR register.This resusts in not having the one cycle latency when the fixed master re-trying access on the slave.
SLOT_CYCLE7:0Maximum Number of Allowed Cycles for a Burst

PRS0.PRASPriority A for Slave

Address
0x4100A080
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
M6PR27:24Master 6 Priority
M5PR23:20Master 5 Priority
M4PR19:16Master 4 Priority
M3PR15:12Master 3 Priority
M2PR11:8Master 2 Priority
M1PR7:4Master 1 Priority
M0PR3:0Master 0 Priority
M7PR31:28Master 7 Priority

PRS0.PRBSPriority B for Slave

Address
0x4100A084
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
M14PR27:24Master 14 Priority
M13PR23:20Master 13 Priority
M12PR19:16Master 12 Priority
M11PR15:12Master 11 Priority
M10PR11:8Master 10 Priority
M9PR7:4Master 9 Priority
M8PR3:0Master 8 Priority
M15PR31:28Master 15 Priority

PRS1.PRASPriority A for Slave

Address
0x4100A088
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
M6PR27:24Master 6 Priority
M5PR23:20Master 5 Priority
M4PR19:16Master 4 Priority
M3PR15:12Master 3 Priority
M2PR11:8Master 2 Priority
M1PR7:4Master 1 Priority
M0PR3:0Master 0 Priority
M7PR31:28Master 7 Priority

PRS1.PRBSPriority B for Slave

Address
0x4100A08C
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
M14PR27:24Master 14 Priority
M13PR23:20Master 13 Priority
M12PR19:16Master 12 Priority
M11PR15:12Master 11 Priority
M10PR11:8Master 10 Priority
M9PR7:4Master 9 Priority
M8PR3:0Master 8 Priority
M15PR31:28Master 15 Priority

PRS2.PRASPriority A for Slave

Address
0x4100A090
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
M6PR27:24Master 6 Priority
M5PR23:20Master 5 Priority
M4PR19:16Master 4 Priority
M3PR15:12Master 3 Priority
M2PR11:8Master 2 Priority
M1PR7:4Master 1 Priority
M0PR3:0Master 0 Priority
M7PR31:28Master 7 Priority

PRS2.PRBSPriority B for Slave

Address
0x4100A094
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
M14PR27:24Master 14 Priority
M13PR23:20Master 13 Priority
M12PR19:16Master 12 Priority
M11PR15:12Master 11 Priority
M10PR11:8Master 10 Priority
M9PR7:4Master 9 Priority
M8PR3:0Master 8 Priority
M15PR31:28Master 15 Priority

PRS3.PRASPriority A for Slave

Address
0x4100A098
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
M6PR27:24Master 6 Priority
M5PR23:20Master 5 Priority
M4PR19:16Master 4 Priority
M3PR15:12Master 3 Priority
M2PR11:8Master 2 Priority
M1PR7:4Master 1 Priority
M0PR3:0Master 0 Priority
M7PR31:28Master 7 Priority

PRS3.PRBSPriority B for Slave

Address
0x4100A09C
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
FieldBitsWhat it does
M14PR27:24Master 14 Priority
M13PR23:20Master 13 Priority
M12PR19:16Master 12 Priority
M11PR15:12Master 11 Priority
M10PR11:8Master 10 Priority
M9PR7:4Master 9 Priority
M8PR3:0Master 8 Priority
M15PR31:28Master 15 Priority

MRCRMaster Remap Control

Address
0x4100A100
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
FieldBitsWhat it does
RCB1515Remap Command Bit for Master 15
  • 0 Disable remapped address decoding for master
  • 1 Enable remapped address decoding for master
RCB1414Remap Command Bit for Master 14
  • 0 Disable remapped address decoding for master
  • 1 Enable remapped address decoding for master
RCB1313Remap Command Bit for Master 13
  • 0 Disable remapped address decoding for master
  • 1 Enable remapped address decoding for master
RCB1212Remap Command Bit for Master 12
  • 0 Disable remapped address decoding for master
  • 1 Enable remapped address decoding for master
RCB1111Remap Command Bit for Master 11
  • 0 Disable remapped address decoding for master
  • 1 Enable remapped address decoding for master
RCB1010Remap Command Bit for Master 10
  • 0 Disable remapped address decoding for master
  • 1 Enable remapped address decoding for master
RCB99Remap Command Bit for Master 9
  • 0 Disable remapped address decoding for master
  • 1 Enable remapped address decoding for master
RCB88Remap Command Bit for Master 8
  • 0 Disable remapped address decoding for master
  • 1 Enable remapped address decoding for master
RCB77Remap Command Bit for Master 7
  • 0 Disable remapped address decoding for master
  • 1 Enable remapped address decoding for master
RCB66Remap Command Bit for Master 6
  • 0 Disable remapped address decoding for master
  • 1 Enable remapped address decoding for master
RCB55Remap Command Bit for Master 5
  • 0 Disable remapped address decoding for master
  • 1 Enable remapped address decoding for master
RCB44Remap Command Bit for Master 4
  • 0 Disable remapped address decoding for master
  • 1 Enable remapped address decoding for master
RCB33Remap Command Bit for Master 3
  • 0 Disable remapped address decoding for master
  • 1 Enable remapped address decoding for master
RCB22Remap Command Bit for Master 2
  • 0 Disable remapped address decoding for master
  • 1 Enable remapped address decoding for master
RCB11Remap Command Bit for Master 1
  • 0 Disable remapped address decoding for master
  • 1 Enable remapped address decoding for master
RCB00Remap Command Bit for Master 0
  • 0 Disable remapped address decoding for master
  • 1 Enable remapped address decoding for master

SFR0Special Function

Address
0x4100A110
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR1Special Function

Address
0x4100A114
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR2Special Function

Address
0x4100A118
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR3Special Function

Address
0x4100A11C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR4Special Function

Address
0x4100A120
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR5Special Function

Address
0x4100A124
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR6Special Function

Address
0x4100A128
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR7Special Function

Address
0x4100A12C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR8Special Function

Address
0x4100A130
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR9Special Function

Address
0x4100A134
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR10Special Function

Address
0x4100A138
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR11Special Function

Address
0x4100A13C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR12Special Function

Address
0x4100A140
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR13Special Function

Address
0x4100A144
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR14Special Function

Address
0x4100A148
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register

SFR15Special Function

Address
0x4100A14C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SFR31:0Special Function Register