PIC32CM6408JH00032 MCLK registers The 8 registers of MCLK (Main Clock), from 0x40000801, with their reset value and every field. The PIC32CM6408JH00032 has 917 registers in 39 peripherals, one page each.
MCLK Main Clock INTENCLRInterrupt Enable Clear
Address 0x40000801
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CKRDY 1 field
Field Bits What it does CKRDY 0 Clock Ready Interrupt Enable
INTENSETInterrupt Enable Set
Address 0x40000802
Reset 0x00
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CKRDY 1 field
Field Bits What it does CKRDY 0 Clock Ready Interrupt Enable
INTFLAGInterrupt Flag Status and Clear
Address 0x40000803
Reset 0x01
Access read/write 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CKRDY 1 field
Field Bits What it does CKRDY 0 Clock Ready
CPUDIVCPU Clock Division
Address 0x40000804
Reset 0x01
Access read/write 7 CPUDIV7 6 CPUDIV6 5 CPUDIV5 4 CPUDIV4 3 CPUDIV3 2 CPUDIV2 1 CPUDIV1 0 CPUDIV0 1 field
Field Bits What it does CPUDIV 7:0 CPU Clock Division Factor1 Divide by 12 Divide by 24 Divide by 48 Divide by 816 Divide by 1632 Divide by 3264 Divide by 64128 Divide by 128
AHBMASKAHB Mask
Address 0x40000810
Reset 0x00001CFF
Access read/write
Size 32-bit 11 fields
Field Bits What it does DIVAS_ 12 DIVAS AHB Clock Mask NVMCTRL_PICACHU_ 11 NVMCTRL_PICACHU AHB Clock Mask PAC_ 10 PAC AHB Clock Mask DMAC_ 7 DMAC AHB Clock Mask HSRAM_ 6 HSRAM AHB Clock Mask NVMCTRL_ 5 NVMCTRL AHB Clock Mask HMATRIXHS_ 4 HMATRIXHS AHB Clock Mask DSU_ 3 DSU AHB Clock Mask HPB2_ 2 HPB2 AHB Clock Mask HPB1_ 1 HPB1 AHB Clock Mask HPB0_ 0 HPB0 AHB Clock Mask
APBAMASKAPBA Mask
Address 0x40000814
Reset 0x00000FFF
Access read/write
Size 32-bit 12 fields
Field Bits What it does FREQM_ 11 FREQM APB Clock Enable EIC_ 10 EIC APB Clock Enable RTC_ 9 RTC APB Clock Enable WDT_ 8 WDT APB Clock Enable GCLK_ 7 GCLK APB Clock Enable SUPC_ 6 SUPC APB Clock Enable OSC32KCTRL_ 5 OSC32KCTRL APB Clock Enable OSCCTRL_ 4 OSCCTRL APB Clock Enable RSTC_ 3 RSTC APB Clock Enable MCLK_ 2 MCLK APB Clock Enable PM_ 1 PM APB Clock Enable PAC_ 0 PAC APB Clock Enable
APBBMASKAPBB Mask
Address 0x40000818
Reset 0x00000007
Access read/write
Size 32-bit 4 fields
Field Bits What it does HMATRIXHS_ 5 HMATRIXHS APB Clock Enable NVMCTRL_ 2 NVMCTRL APB Clock Enable DSU_ 1 DSU APB Clock Enable PORT_ 0 PORT APB Clock Enable
APBCMASKAPBC Mask
Address 0x4000081C
Reset 0x00000000
Access read/write
Size 32-bit 17 fields
Field Bits What it does CCL_ 23 CCL APB Clock Enable PTC_ 22 PTC APB Clock Enable AC_ 20 AC APB Clock Enable ADC0_ 17 ADC0 APB Clock Enable TC4_ 16 TC4 APB Clock Enable TC3_ 15 TC3 APB Clock Enable TC2_ 14 TC2 APB Clock Enable TC1_ 13 TC1 APB Clock Enable TC0_ 12 TC0 APB Clock Enable TCC2_ 11 TCC2 APB Clock Enable TCC1_ 10 TCC1 APB Clock Enable TCC0_ 9 TCC0 APB Clock Enable SERCOM3_ 4 SERCOM3 APB Clock Enable SERCOM2_ 3 SERCOM2 APB Clock Enable SERCOM1_ 2 SERCOM1 APB Clock Enable SERCOM0_ 1 SERCOM0 APB Clock Enable EVSYS_ 0 EVSYS APB Clock Enable