The 22 registers of ADC1 (Analog Digital Converter), from 0x42004800, with their reset value and every field. The PIC32CM6408MC00048 has 1146 registers in 44 peripherals, one page each.
ADC1 Analog Digital Converter
CTRLAControl A
Address
0x42004800
Reset
0x00
Access
read/write
7ONDEMAND
6RUNSTDBY
5SLAVEEN
4–
3–
2–
1ENABLE
0SWRST
5 fields
Field
Bits
What it does
ONDEMAND
7
On Demand Control
RUNSTDBY
6
Run During Standby
SLAVEEN
5
Slave Enable
ENABLE
1
Enable
SWRST
0
Software Reset
CTRLBControl B
Address
0x42004801
Reset
0x00
Access
read/write
7–
6–
5–
4–
3–
2PRESCALER2
1PRESCALER1
0PRESCALER0
1 field
Field
Bits
What it does
PRESCALER
2:0
Prescaler Configuration
0 Peripheral clock divided by 2
1 Peripheral clock divided by 4
2 Peripheral clock divided by 8
3 Peripheral clock divided by 16
4 Peripheral clock divided by 32
5 Peripheral clock divided by 64
6 Peripheral clock divided by 128
7 Peripheral clock divided by 256
REFCTRLReference Control
Address
0x42004802
Reset
0x00
Access
read/write
7REFCOMP
6–
5–
4–
3REFSEL3
2REFSEL2
1REFSEL1
0REFSEL0
2 fields
Field
Bits
What it does
REFCOMP
7
Reference Buffer Offset Compensation Enable
REFSEL
3:0
Reference Selection
0 Internal Voltage Reference
1 1/1.6 VDDANA
2 1/2 VDDANA
3 External Voltage Reference A (shared with DAC)
4 DAC Internal Output
5 VDDANA
EVCTRLEvent Control
Address
0x42004803
Reset
0x00
Access
read/write
7–
6–
5WINMONEO
4RESRDYEO
3STARTINV
2FLUSHINV
1STARTEI
0FLUSHEI
6 fields
Field
Bits
What it does
WINMONEO
5
Window Monitor Event Out
RESRDYEO
4
Result Ready Event Out
STARTINV
3
Start Event Invert Enable
FLUSHINV
2
Flush Event Invert Enable
STARTEI
1
Start Conversion Event Input Enable
FLUSHEI
0
Flush Event Input Enable
INTENCLRInterrupt Enable Clear
Address
0x42004804
Reset
0x00
Access
read/write
7–
6–
5–
4–
3–
2WINMON
1OVERRUN
0RESRDY
3 fields
Field
Bits
What it does
WINMON
2
Window Monitor Interrupt Disable
OVERRUN
1
Overrun Interrupt Disable
RESRDY
0
Result Ready Interrupt Disable
INTENSETInterrupt Enable Set
Address
0x42004805
Reset
0x00
Access
read/write
7–
6–
5–
4–
3–
2WINMON
1OVERRUN
0RESRDY
3 fields
Field
Bits
What it does
WINMON
2
Window Monitor Interrupt Enable
OVERRUN
1
Overrun Interrupt Enable
RESRDY
0
Result Ready Interrupt Enable
INTFLAGInterrupt Flag Status and Clear
Address
0x42004806
Reset
0x00
Access
read/write
7–
6–
5–
4–
3–
2WINMON
1OVERRUN
0RESRDY
3 fields
Field
Bits
What it does
WINMON
2
Window Monitor Interrupt Flag
OVERRUN
1
Overrun Interrupt Flag
RESRDY
0
Result Ready Interrupt Flag
SEQSTATUSSequence Status
Address
0x42004807
Reset
0x00
Access
read only
7SEQBUSY
6–
5–
4SEQSTATE4
3SEQSTATE3
2SEQSTATE2
1SEQSTATE1
0SEQSTATE0
2 fields
Field
Bits
What it does
SEQBUSY
7
Sequence Busy
SEQSTATE
4:0
Sequence State
INPUTCTRLInput Control
Address
0x42004808
Reset
0x0000
Access
read/write
Size
16-bit
2 fields
Field
Bits
What it does
MUXNEG
12:8
Negative Mux Input Selection
0 ADC AIN0 Pin
1 ADC AIN1 Pin
2 ADC AIN2 Pin
3 ADC AIN3 Pin
4 ADC AIN4 Pin
5 ADC AIN5 Pin
24 Internal Ground
MUXPOS
4:0
Positive Mux Input Selection
0 ADC AIN0 Pin
1 ADC AIN1 Pin
2 ADC AIN2 Pin
3 ADC AIN3 Pin
4 ADC AIN4 Pin
5 ADC AIN5 Pin
6 ADC AIN6 Pin
7 ADC AIN7 Pin
8 ADC AIN8 Pin
9 ADC AIN9 Pin
10 ADC AIN10 Pin
11 ADC AIN11 Pin
25 Internal Voltage Reference
26 1/4 Scaled VDDCORE Supply
27 1/4 Scaled VDDANA Supply
CTRLCControl C
Address
0x4200480A
Reset
0x0000
Access
read/write
Size
16-bit
8 fields
Field
Bits
What it does
DUALSEL
13:12
Dual Mode Trigger Selection
0 Start event or software trigger will start a conversion on both ADCs
1 START event or software trigger will alternatively start a conversion on ADC0 and ADC1
WINMODE
10:8
Window Monitor Mode
0 No window mode (default)
1 RESULT > WINLT
2 RESULT < WINUT
3 WINLT < RESULT < WINUT
4 !(WINLT < RESULT < WINUT)
R2R
7
Rail-to-Rail mode enable
RESSEL
5:4
Conversion Result Resolution
0 12-bit result
1 Accumulation or Oversampling and Decimation modes
BETA