PIC32CX1012BZ24032 CFG registers

The 52 registers of CFG, from 0x44000000, with their reset value and every field. The PIC32CX1012BZ24032 has 1802 registers in 52 peripherals, one page each.

CFG

CFGCON0

Address
0x44000000
Reset
0x7100000B
Access
read/write
Size
32-bit
26 fields
FieldBitsWhat it does
FRECCDIS30Flex RAM ECC Control
FECCCON29:28Flash ECC Control
INT0P26INT0P Polarity
INT0E25INT0 Enable
PCM24PCHE I/D Cacheable Mode
SLRTEN122SLRT Enable for SERCOM1
SLRTEN021SLRT Enable for SERCOM0
HPLUGDIS20Hot Plugging Disable
SMBUSEN118SMBus Enable for SERCOM1
SMBUSEN017SMBus Enable for SERCOM0
VBCMODE16VBC Operating Mode
CFGCLOCK15:14Configuration Register Lock
IOLOCK13IO LOCK
PMDLOCK12Peripheral Module Disable (PMD) LOCK
PGLCOK11Permission Group LOCK
PMULOCK10PMU Controller Register LOCK
RTCOUT_ALTEN9RTCOUT Alternate Enable
RTCIN0_ALTEN8RTCIN0 Alternate Enable
CPENFILT7ADC CP Filter Enable
ACCMP1_ALTEN6AC CMP1 Alternate Enable
GPSOSCE5GPIO/SOSC Enable
ADCPOVR4ADC Charge Pump Override
JTAGEN3JTAG Enable
TROEN2Trace Output Enable
SWOEN1SWO enable on 2-wire debug interface
TDOEN0TDO enable for 2-wire JTAG

CFGCON0CLRBit clear register

Address
0x44000004
Reset
0x00000000
Access
read/write
Size
32-bit

CFGCON0SETBit set register

Address
0x44000008
Reset
0x00000000
Access
read/write
Size
32-bit

CFGCON0INVBit invert register

Address
0x4400000C
Reset
0x00000000
Access
read/write
Size
32-bit

CFGCON1

Address
0x44000010
Reset
0x1700443B
Access
read/write
Size
32-bit
19 fields
FieldBitsWhat it does
CLKZBREF30External Reference Clock ZB Enable
QSPIDDRM29QSPI DDR Mode Clock Enable
WDTPSS28:24Watchdog Timer Post-scale Select Sleep
I2CDSEL122I2C Delay Select for SERCOM1
I2CDSEL021I2C Delay Select for SERCOM0
CCL_OE20CCL Pads (via PPS) Output Enable
SCOM1_HSEN18SERCOM1 (Direct)High Speed Pin Enable
SCOM0_HSEN17SERCOM0 (Direct)High Speed Pin Enable
QSCHE_EN15QSPI Address Space Cache Attribute
SMCLR14Selects CRU handling of MCLR Control
SLRCTRL112I2C Slew Rate Control for SERCOM1
SLRCTRL011I2C Slew Rate Control for SERCOM0
CLASSBDIS10Disable CLASSB Device Functionality
CMP1_OE9Analog Comparator-1 Output Enable
CMP0_OE8Analog Comparator-0 Output Enable
ZBTWKSYS7ZBT Subsystem External Wake-up source
TRCEN5Trace Enable
ICESEL4:3EMUC/EMUD Communication Channel Select
DEBUG1:0Background Debugger Access Selection

CFGCON1CLRBit clear register

Address
0x44000014
Reset
0x00000000
Access
read/write
Size
32-bit

CFGCON1SETBit set register

Address
0x44000018
Reset
0x00000000
Access
read/write
Size
32-bit

CFGCON1INVBit invert register

Address
0x4400001C
Reset
0x00000000
Access
read/write
Size
32-bit

CFGCON2

Address
0x44000020
Reset
0x7F7FFF38
Access
read/write
Size
32-bit
16 fields
FieldBitsWhat it does
DMTCNT30:26Dead Man Timer Count Select
WDTWINSZ25:24Watchdog Timer Window Size
WDTEN23Watchdog Timer Enable
WINDIS22Windowed Watchdog Timer Disable
WDTSPGM21Watchdog Timer Stop during Flash Programming
WDTPSR20:16Watchdog Timer Post-scale Select Run
FSCMEN15Fail-Safe Clock Monitor Enable
CKSWEN14Software Clock Switching Enable
WAKE2SPD132-Speed startup enabled in Sleep mode
SOSCSEL12SOSC Selection Configuration
WDTRMCS11:10WDT RUN Mode Clock Select
POSCMOD9:8Primary Oscillator Configuration
PMUTEST_VDD_EN7PMU Test Output or VDD/2 Enable via ADC IE12
DMTINTV5:3Dead Man Timer Count Window Interval
ACMP_CYCLE2:0AC SIB Comparator Result Wait Cycles
DMTEN31Dead Man Timer Enable

CFGCON2CLRBit clear register

Address
0x44000024
Reset
0x00000000
Access
read/write
Size
32-bit

CFGCON2SETBit set register

Address
0x44000028
Reset
0x00000000
Access
read/write
Size
32-bit

CFGCON2INVBit invert register

Address
0x4400002C
Reset
0x00000000
Access
read/write
Size
32-bit

CFGCON4

Address
0x44000040
Reset
0x840E4000
Access
read/write
Size
32-bit
16 fields
FieldBitsWhat it does
UVREGROVR29ULPVREG Retention Mode Override
DSEN28Deep Sleep Bit Enable
DSWDTEN27Deep Sleep Watchdog Timer Enable
DSWDTOSC26Deep Sleep Watchdog Timer Reference Clock Select
DSWDTPS25:21Deep Sleep Watchdog Timer Postscale Select
DSZPBOREN20Deep Sleep Zero-Power BOR Enable
CPEN_DLY19:17Charge-pump ready digital delay
RTCEFTYPE16RTC Event Type
LPCLK_MOD15LPCLK modifier in counter/delay mode
VBKP_DIVSEL14VDDBUKPCORE LPCLK Clock Divider Selection
VBKP_32KCSEL13:12VDDBUKPCORE 32KHz clock source selection
VBKP_1KCSEL11VDDBUKPCORE LPCLK Clock Selection
RTCEVENT_EN10Pad Output Enable for MCHP legacy RTC event output
RTCEVENT_SEL9:8RTC Event Selection
SOSCCFG7:0SOSC Configuration
RTCNTM_CSEL31RTC Counter Mode Clock Select

CFGCON4CLRBit clear register

Address
0x44000044
Reset
0x00000000
Access
read/write
Size
32-bit

CFGCON4SETBit set register

Address
0x44000048
Reset
0x00000000
Access
read/write
Size
32-bit

CFGCON4INVBit invert register

Address
0x4400004C
Reset
0x00000000
Access
read/write
Size
32-bit

CFGPGQOS

Address
0x44000050
Reset
0xE040004C
Access
read/write
Size
32-bit
12 fields
FieldBitsWhat it does
FCQOS29:28FC Controller QOS Control
DSUPG25:24DSU Permission Group
ICMQOS23:22ICM QOS Control
ICMPG21:20ICM Permission Group
ADCQOS19:18ADC Controller QOS Control
ADCPG17:16ADC Controller Permission Group
DMAPG9:8DMA (Rd/Wr) Permission Group
ICDJQOS7:6ICD-JTAG Bus QOS Control
ICDJPG5:4ICD-JTAG Permission Group
CPUQOS3:2CPU I/D and System Bus QOS Control
CPUPG1:0CPU (Code) Permission Group
WISIBQOS31:30Wireless SIB QOS Control

CFGPGQOSCLRBit clear register

Address
0x44000054
Reset
0x00000000
Access
read/write
Size
32-bit

CFGPGQOSSETBit set register

Address
0x44000058
Reset
0x00000000
Access
read/write
Size
32-bit

CFGPGQOSINVBit invert register

Address
0x4400005C
Reset
0x00000000
Access
read/write
Size
32-bit

CFGPCLKGEN1

Address
0x44000060
Reset
0x00000000
Access
read/write
Size
32-bit
14 fields
FieldBitsWhat it does
CM4TCSEL30:28CM4T Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
TC23CD27TC2/3 Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK
TC23CSEL26:24TC2/3 Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
TCC12CD23TCC1/2 Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK
TCC12CSEL22:20TCC1/2 Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
S01CD15SERCOM0/1 Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK
SERCOM01CSEL14:12SERCOM0/1 Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
MCD11FREQMMC Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK
FREQMMCSEL10:8FREQMMC Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
RCD7FREQMRC Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK
FREQMRCSEL6:4FREQMRC Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
EICCD3EIC Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK
EICCSEL2:0EIC Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
CM4TD31CM4T Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK

CFGPCLKGEN1CLRBit clear register

Address
0x44000064
Reset
0x00000000
Access
read/write
Size
32-bit

CFGPCLKGEN1SETBit set register

Address
0x44000068
Reset
0x00000000
Access
read/write
Size
32-bit

CFGPCLKGEN1INVBit invert register

Address
0x4400006C
Reset
0x00000000
Access
read/write
Size
32-bit

CFGPCLKGEN2

Address
0x44000070
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
FieldBitsWhat it does
EVSYSC8SEL30:28EVSYSC8 Peripheral Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
C7D27C7D Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK
EVSYSC7SEL26:24EVSYSC7 Peripheral Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
C6D23EVSYSC6 Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK
EVSYSC6SEL22:20EVSYSC6 Peripheral Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
C5D19EVSYSC5 Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK
EVSYSC5SEL18:16EVSYSC5 Peripheral Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
C4D15EVSYSC4 Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK
EVSYSC4SEL14:12EVSYSC4 Peripheral Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
C3D11EVSYSC3 Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK
EVSYSC3SEL10:8EVSYSC3 Peripheral Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
C2D7EVSYSC2 Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK
EVSYSC2SEL6:4EVSYSC2 Peripheral Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
C1D3EVSYSC1 Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK
EVSYSC1SEL2:0EVSYSC1 Peripheral Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
C8D31C8D Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK

CFGPCLKGEN2CLRBit clear register

Address
0x44000074
Reset
0x00000000
Access
read/write
Size
32-bit

CFGPCLKGEN2SETBit set register

Address
0x44000078
Reset
0x00000000
Access
read/write
Size
32-bit

CFGPCLKGEN2INVBit invert register

Address
0x4400007C
Reset
0x00000000
Access
read/write
Size
32-bit

CFGPCLKGEN3

Address
0x44000080
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
FieldBitsWhat it does
TC1CSEL30:28TC1 Peripheral Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
TC0CD27TC0 Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK
TC0CSEL26:24TC0 Peripheral Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
TCC0CD23TCC0 Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK
TCC0CSEL22:20TCC0 Peripheral Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
ACCD19AC Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK
ACCLKSEL18:16AC Peripheral Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
C12D15C12D Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK
EVSYSC12SEL14:12EVSYSC12 Peripheral Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
C11D11C11D Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK
EVSYSC11SEL10:8EVSYSC11 Peripheral Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
C10D7C10D Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK
EVSYSC10SEL6:4EVSYSC10 Peripheral Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
C9D3C9D Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK
EVSYSC9SEL2:0EVSYSC9 Peripheral Clock Selection
  • 0 No Clock
  • 1 Reference Clock 1
  • 2 Reference Clock 2
  • 3 Reference Clock 3
  • 4 Reference Clock 4
  • 5 Reference Clock 5
  • 6 Reference Clock 6
  • 7 32 KHz Low Power Clock
TC1CD31TC1 Clock Disable
  • 0 Disable PGCLK
  • 1 Enable PGCLK

CFGPCLKGEN3CLRBit clear register

Address
0x44000084
Reset
0x00000000
Access
read/write
Size
32-bit

CFGPCLKGEN3SETBit set register

Address
0x44000088
Reset
0x00000000
Access
read/write
Size
32-bit

CFGPCLKGEN3INVBit invert register

Address
0x4400008C
Reset
0x00000000
Access
read/write
Size
32-bit

IDDevice ID

Address
0x44000090
Reset
0x00000000
Access
read only
Size
32-bit

USER_ID

Address
0x440000A0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
USER_ID15:0User unique ID, readable using the JTAG USER_ID instruction

USER_IDCLRBit clear register

Address
0x440000A4
Reset
0x00000000
Access
read/write
Size
32-bit

USER_IDSETBit set register

Address
0x440000A8
Reset
0x00000000
Access
read/write
Size
32-bit

USER_IDINVBit invert register

Address
0x440000AC
Reset
0x00000000
Access
read/write
Size
32-bit

SYSKEY

Address
0x440000B0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
SYSKEY31:0System Key

PMD1

Address
0x440000C0
Reset
0x00000000
Access
read/write
Size
32-bit
10 fields
FieldBitsWhat it does
SQIMD29SQI Module Disable
RTCCMD16RTCC Module Disable
ADCSARMD8Shared ADC SAR Core Module Disable
ADCMD7ADC Controller Module Disable
ACMD6AC Module Disable
PLVDMD4PLVD Module Disable
LPAMD3RF LPA Module Disable
MPAMD2RF MPA Module Disable
BTMD1Bluetooth Module Disable
ZBMD0ZigBee Module Disable

PMD1CLRBit clear register

Address
0x440000C4
Reset
0x00000000
Access
read/write
Size
32-bit

PMD1SETBit set register

Address
0x440000C8
Reset
0x00000000
Access
read/write
Size
32-bit

PMD1INVBit invert register

Address
0x440000CC
Reset
0x00000000
Access
read/write
Size
32-bit

PMD2

Address
0x440000D0
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
FieldBitsWhat it does
REFO3MD30Reference (Clock) Out 3 Module Disable
REFO2MD29Reference (Clock) Out 2 Module Disable
REFO1MD28Reference (Clock) Out 1 Module Disable
REFO6MD25Reference (Clock) Out 6 Module Disable
REFO5MD24Reference (Clock) Out 5 Module Disable
REFO4MD31Reference (Clock) Out 4 Module Disable

PMD2CLRBit clear register

Address
0x440000D4
Reset
0x00000000
Access
read/write
Size
32-bit

PMD2SETBit set register

Address
0x440000D8
Reset
0x00000000
Access
read/write
Size
32-bit

PMD2INVBit invert register

Address
0x440000DC
Reset
0x00000000
Access
read/write
Size
32-bit

PMD3

Address
0x440000E0
Reset
0x00000000
Access
read/write
Size
32-bit
13 fields
FieldBitsWhat it does
TCC2MD14TCC2 Module Disable
TCC1MD13TCC1 Module Disable
TCC0MD12TCC0 Module Disable
TC3MD11TC3 Module Disable
TC2MD10TC2 Module Disable
TC1MD9TC1 Module Disable
TC0MD8TC0 Module Disable
AESMD7AES Module Disable
RNGMD6TRNG Module Disable
PUKCCMD5PUKCC Module Disable
ICMMD4ICM Module Disable
SER2MD1SERCOM2 Module Disable
SER1MD0SERCOM1 Module Disable

PMD3CLRBit clear register

Address
0x440000E4
Reset
0x00000000
Access
read/write
Size
32-bit

PMD3SETBit set register

Address
0x440000E8
Reset
0x00000000
Access
read/write
Size
32-bit

PMD3INVBit invert register

Address
0x440000EC
Reset
0x00000000
Access
read/write
Size
32-bit

MISCSTAT

Address
0x44000100
Reset
0x01000081
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
CLDORDY9CLDO Ready

BCFG0

Address
0x44000200
Reset
0x00000000
Access
read only
Size
32-bit
4 fields
FieldBitsWhat it does
SIGN29Flash SIGN
CP28Boot Code Protect
PCSCMODE1PCHE Single cache Mode
BINFOVALID031First 256-bit BCFG information Valid