The 56 registers of AES (Advanced Encryption Standard), from 0x44000000, with their reset value and every field. The PIC32CX1025MTSH128 has 2920 registers in 63 peripherals, one page each.
AES Advanced Encryption Standard
AES_CRControl Register
Address
0x44000000
Reset
0x00000000
Access
write only
Size
32-bit
4 fields
Field
Bits
What it does
UNLOCK
24
Unlock Processing
SWRST
8
Software Reset
KSWP
1
Key Swap
START
0
Start Processing
AES_MRMode Register
Address
0x44000004
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
CKEY
23:20
Key
14 This field must be written with 0xE the first time AES_MR is programmed. For subsequent programming of AES_MR, any value can be written, including that of 0xE. Always reads as 0.
CFBS
18:16
Cipher Feedback Data Size
0 128-bit
1 64-bit
2 32-bit
3 16-bit
4 8-bit
LOD
15
Last Output Data Mode
OPMOD
14:12
Operating Mode
0 ECB: Electronic Codebook mode
1 CBC: Cipher Block Chaining mode
2 OFB: Output Feedback mode
3 CFB: Cipher Feedback mode
4 CTR: Counter mode (16-bit internal counter)
5 GCM: Galois/Counter mode
KEYSIZE
11:10
Key Size
0 AES Key Size is 128 bits
1 AES Key Size is 192 bits
2 AES Key Size is 256 bits
SMOD
9:8
Start Mode
0 Manual Mode
1 Auto Mode
2 AES_IDATAR0 access only Auto Mode (PDC)
PROCDLY
7:4
Processing Delay
DUALBUFF
3
Dual Input Buffer
0 AES_IDATARx cannot be written during processing of previous block.
1 AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files.
Unspecified Register Access (cleared by writing SWRST in AES_CR)
0 Input Data register written during the data processing when SMOD = 2 mode.
1 Output Data register read during the data processing.
2 Mode register written during the data processing.
3 Output Data register read during the sub-keys generation.
4 Mode register written during the sub-keys generation.
5 Write-only register read access.
URAD
8
Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR)
TXBUFE
4
TX Buffer Empty (cleared by writing AES_TCR or AES_TNCR)
RXBUFF
3
RX Buffer Full (cleared by writing AES_RCR or AES_RNCR)
ENDTX
2
End of TX Buffer (cleared by writing AES_TCR or AES_TNCR)
ENDRX
1
End of RX Buffer (cleared by writing AES_RCR or AES_RNCR)
DATRDY
0
Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx)
AES_KEYWR0Key Word Register
Address
0x44000020
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
KEYW
31:0
Key Word
AES_KEYWR1Key Word Register
Address
0x44000024
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
KEYW
31:0
Key Word
AES_KEYWR2Key Word Register
Address
0x44000028
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
KEYW
31:0
Key Word
AES_KEYWR3Key Word Register
Address
0x4400002C
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
KEYW
31:0
Key Word
AES_KEYWR4Key Word Register
Address
0x44000030
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
KEYW
31:0
Key Word
AES_KEYWR5Key Word Register
Address
0x44000034
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
KEYW
31:0
Key Word
AES_KEYWR6Key Word Register
Address
0x44000038
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
KEYW
31:0
Key Word
AES_KEYWR7Key Word Register
Address
0x4400003C
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
KEYW
31:0
Key Word
AES_IDATAR0Input Data Register
Address
0x44000040
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
IDATA
31:0
Input Data Word
AES_IDATAR1Input Data Register
Address
0x44000044
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
IDATA
31:0
Input Data Word
AES_IDATAR2Input Data Register
Address
0x44000048
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
IDATA
31:0
Input Data Word
AES_IDATAR3Input Data Register
Address
0x4400004C
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
IDATA
31:0
Input Data Word
AES_ODATAR0Output Data Register
Address
0x44000050
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
ODATA
31:0
Output Data
AES_ODATAR1Output Data Register
Address
0x44000054
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
ODATA
31:0
Output Data
AES_ODATAR2Output Data Register
Address
0x44000058
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
ODATA
31:0
Output Data
AES_ODATAR3Output Data Register
Address
0x4400005C
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
ODATA
31:0
Output Data
AES_IVR0Initialization Vector Register
Address
0x44000060
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
IV
31:0
Initialization Vector
AES_IVR1Initialization Vector Register
Address
0x44000064
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
IV
31:0
Initialization Vector
AES_IVR2Initialization Vector Register
Address
0x44000068
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
IV
31:0
Initialization Vector
AES_IVR3Initialization Vector Register
Address
0x4400006C
Reset
0x00000000
Access
write only
Size
32-bit
1 field
Field
Bits
What it does
IV
31:0
Initialization Vector
AES_AADLENRAdditional Authenticated Data Length Register
Address
0x44000070
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
AADLEN
31:0
Additional Authenticated Data Length
AES_CLENRPlaintext/Ciphertext Length Register
Address
0x44000074
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
CLEN
31:0
Plaintext/Ciphertext Length
AES_GHASHR0GCM Intermediate Hash Word Register
Address
0x44000078
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
GHASH
31:0
Intermediate GCM Hash Word x
AES_GHASHR1GCM Intermediate Hash Word Register
Address
0x4400007C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
GHASH
31:0
Intermediate GCM Hash Word x
AES_GHASHR2GCM Intermediate Hash Word Register
Address
0x44000080
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
GHASH
31:0
Intermediate GCM Hash Word x
AES_GHASHR3GCM Intermediate Hash Word Register
Address
0x44000084
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
GHASH
31:0
Intermediate GCM Hash Word x
AES_TAGR0GCM Authentication Tag Word Register
Address
0x44000088
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
TAG
31:0
GCM Authentication Tag x
AES_TAGR1GCM Authentication Tag Word Register
Address
0x4400008C
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
TAG
31:0
GCM Authentication Tag x
AES_TAGR2GCM Authentication Tag Word Register
Address
0x44000090
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
TAG
31:0
GCM Authentication Tag x
AES_TAGR3GCM Authentication Tag Word Register
Address
0x44000094
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
TAG
31:0
GCM Authentication Tag x
AES_CTRRGCM Encryption Counter Value Register
Address
0x44000098
Reset
0x00000000
Access
read only
Size
32-bit
1 field
Field
Bits
What it does
CTR
31:0
GCM Encryption Counter
AES_GCMHR0GCM H Word Register
Address
0x4400009C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
H
31:0
GCM H Word x
AES_GCMHR1GCM H Word Register
Address
0x440000A0
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
H
31:0
GCM H Word x
AES_GCMHR2GCM H Word Register
Address
0x440000A4
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
H
31:0
GCM H Word x
AES_GCMHR3GCM H Word Register
Address
0x440000A8
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
H
31:0
GCM H Word x
AES_EMRExtended Mode Register
Address
0x440000B0
Reset
0x00000000
Access
read/write
Size
32-bit
11 fields
Field
Bits
What it does
ALGO
24
Encryption Algorithm
0 The AES algorithm is used for encryption.
1 The ARIA algorithm is used for encryption.
NHEAD
23:16
IPSec Next Header
PADLEN
15:8
Auto Padding Length
PKRS
7
Private Key Internal Register Select
PKWL
6
Private Key Write Lock
PLIPD
5
Protocol Layer Improved Performance Decipher
PLIPEN
4
Protocol Layer Improved Performance Enable
KSEL
2
Key Selection
APM
1
Auto Padding Mode
APEN
0
Auto Padding Enable
BPE
31
Block Processing End
AES_BCNTByte Counter Register
Address
0x440000B4
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
BCNT
31:0
Auto Padding Byte Counter
AES_WPMRWrite Protection Mode Register
Address
0x440000E4
Reset
0x00000000
Access
read/write
Size
32-bit
6 fields
Field
Bits
What it does
ACTION
7:5
Action on Abnormal Event Detection
0 No action (stop or clear key) is performed when one of PKRPVS, WPVS, CGD, SEQE, or SWE flags is set.
1 If a processing is in progress when the AES_WPSR.PKRPVS/WPVS/SWE event detection occurs, the current processing is ended normally but no other processing is started while a AES_CR.UNLOCK command is issued.
2 If a processing is in progress when the AES_WPSR.CGD/SEQE event detection occurs, the current processing is ended normally but no other processing is started while a AES_CR.UNLOCK command is issued.
3 If a processing is in progress when the AES_WPSR.PKRPVS/WPVS/CGD/SEQE/SWE events detection occurs, the current processing is ended normally but no other processing is started while a AES_CR.UNLOCK command is issued.
4 If a processing is in progress when the AES_WPSR.PKRPVS/WPVS/SWE events detection occurs, the current processing is ended normally but no other processing is started while a AES_CR.UNLOCK command is issued. Moreover, the AES_KEYWRx key is immediately cleared.
5 If a processing is in progress when the AES_WPSR.CGD/SEQE events detection occurs, the current processing is ended normally but no other processing is started while a AES_CR.UNLOCK command is issued. Moreover, the AES_KEYWRx key is immediately cleared.
6 If a processing is in progress when the AES_WPSR.PKRPVS/WPVS/CGD/SEQE/SWE events detection occurs, the current processing is ended normally but no other processing is started while a AES_CR.UNLOCK command is issued. Moreover, the AES_KEYWRx key is immediately cleared.
FIRSTE
4
First Error Report Enable
WPCREN
2
Write Protection Control Enable
WPITEN
1
Write Protection Interruption Enable
WPEN
0
Write Protection Configuration Enable
WPKEY
31:8
Write Protection Key
4277587 Writing any other value in this field aborts the write operation of the WPEN,WPITEN,WPCREN bits. Always reads as 0.
AES_WPSRWrite Protection Status Register
Address
0x440000E8
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
Field
Bits
What it does
SWETYP
27:24
Software Error Type (cleared on read)
0 A write-only register has been read (Warning).
1 AES is enabled and a write access has been performed on a read-only register (Warning).
2 Access to an undefined address (Warning).
3 Abnormal use of AES_CR.START command when DMA access is configured.
4 A key write, init value write, output data read, AES_MR and AES_EMR write, GCM configuration registers write, AES_BCNT write, Private Key bus access has been performed while a current processing is in progress (abnormal).
5 A tentative of start is required while the key is not fully loaded into the AES_KEYWRx registers.
WPVSRC
15:8
Write Protection Violation Source
PKRPVS
4
Private Key Internal Register Protection Violation Status (cleared on read)
SWE
3
Software Control Error (cleared on read)
SEQE
2
Internal Sequencer Error (cleared on read)
CGD
1
Clock Glitch Detected (cleared on read)
WPVS
0
Write Protection Violation Status (cleared on read)
ECLASS
31
Software Error Class (cleared on read)
0 An abnormal access that does not affect system functionality
1 An access is performed into key, input data, control registers while the AES is performing an encryption/decryption or a start is request by software or DMA while the key is not fully configured.
AES_RPRReceive Pointer Register
Address
0x44000100
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXPTR
31:0
Receive Pointer Register
AES_RCRReceive Counter Register
Address
0x44000104
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXCTR
15:0
Receive Counter Register
AES_TPRTransmit Pointer Register
Address
0x44000108
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXPTR
31:0
Transmit Counter Register
AES_TCRTransmit Counter Register
Address
0x4400010C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXCTR
15:0
Transmit Counter Register
AES_RNPRReceive Next Pointer Register
Address
0x44000110
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXNPTR
31:0
Receive Next Pointer
AES_RNCRReceive Next Counter Register
Address
0x44000114
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXNCTR
15:0
Receive Next Counter
AES_TNPRTransmit Next Pointer Register
Address
0x44000118
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXNPTR
31:0
Transmit Next Pointer
AES_TNCRTransmit Next Counter Register
Address
0x4400011C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXNCTR
15:0
Transmit Counter Next
AES_PTCRTransfer Control Register
Address
0x44000120
Reset
0x00000000
Access
write only
Size
32-bit
9 fields
Field
Bits
What it does
ERRCLR
24
Transfer Bus Error Clear
TXCBDIS
19
Transmitter Circular Buffer Disable
TXCBEN
18
Transmitter Circular Buffer Enable
RXCBDIS
17
Receiver Circular Buffer Disable
RXCBEN
16
Receiver Circular Buffer Enable
TXTDIS
9
Transmitter Transfer Disable
TXTEN
8
Transmitter Transfer Enable
RXTDIS
1
Receiver Transfer Disable
RXTEN
0
Receiver Transfer Enable
AES_PTSRTransfer Status Register
Address
0x44000124
Reset
0x00000000
Access
read only
Size
32-bit
5 fields
Field
Bits
What it does
ERR
24
Transfer Bus Error
TXCBEN
18
Transmitter Circular Buffer Enable
RXCBEN
16
Receiver Circular Buffer Enable
TXTEN
8
Transmitter Transfer Enable
RXTEN
0
Receiver Transfer Enable
AES_PWPMRWrite Protection Mode Register
Address
0x44000128
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
WPCREN
2
Write Protection Control Register Enable
WPCTREN
1
Write Protection Counter Registers Enable
WPPTREN
0
Write Protection Pointer Registers Enable
WPKEY
31:8
Write Protection Key
5260355 Writing any other value in this field aborts the write operation. Always reads as 0.