PIC32CX1025MTSH128 CMCC1 registers

The 11 registers of CMCC1 (Cortex-M Cache Controller), from 0x4600C000, with their reset value and every field. The PIC32CX1025MTSH128 has 2920 registers in 63 peripherals, one page each.

CMCC1 Cortex-M Cache Controller

CMCC_TYPECache Controller Type Register

Address: 0x4600C000
Reset: 0x00000000
Access: read only
Size: 32-bit

9 fields

Field	Bits	What it does
CLSIZE	13:11	Cache LIne Size `0` Cache line size is 4 bytes `1` Cache line size is 8 bytes `2` Cache line size is 16 bytes `3` Cache line size is 32 bytes
CSIZE	10:8	Data Cache Size `0` Cache size is 1 Kbyte `1` Cache size is 2 Kbytes `2` Cache size is 4 Kbytes `3` Cache size is 8 Kbytes `4` Cache size is 16 Kbytes `5` Cache size is 32 Kbytes `6` Cache size is 64 Kbytes
LCKDOWN	7	Lockdown Supported
WAYNUM	6:5	Number of Ways `0` Direct Mapped Cache `1` 2-way set associative `2` 4-way set associative `3` 8-way set associative
RRP	4	Random Selection Policy Supported
LRUP	3	Least Recently Used Policy Supported
RANDP	2	Random Selection Policy Supported
GCLK	1	Dynamic Clock Gating Supported
AP	0	Access Port Access Allowed

CMCC_CFGConfiguration Register

Address: 0x4600C004
Reset: 0x00000000
Access: read/write
Size: 32-bit

5 fields

Field	Bits	What it does
LOCK	8	Configuration Lock Until Next System Reset (Write-once)
PRGCSIZE	6:4	Programmable Cache Size
DCDIS	2	Data Caching Disable
ICDIS	1	Instruction Caching Disable
GCLKDIS	0	Disable Clock Gating

CMCC_CTRLControl Register

Address: 0x4600C008
Reset: 0x00000000
Access: write only
Size: 32-bit

2 fields

Field	Bits	What it does
LOCK	8	Control Lock Until Next System Reset (Write-once)
CEN	0	Cache Controller Enable

CMCC_SRStatus Register

Address: 0x4600C00C
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
CSTS	0	Cache Controller Status

CMCC_MAINT0Maintenance Register 0

Address: 0x4600C020
Reset: 0x00000000
Access: write only
Size: 32-bit

1 field

Field	Bits	What it does
INVALL	0	Cache Controller Invalidate All

CMCC_MAINT1Maintenance Register 1

Address: 0x4600C024
Reset: 0x00000000
Access: write only
Size: 32-bit

2 fields

Field	Bits	What it does
INDEX	10:4	Invalidate Index
WAY	31:30	Invalidate Way `0` Way 0 is selection for index invalidation. `1` Way 1 is selection for index invalidation. `2` Way 2 is selection for index invalidation. `3` Way 3 is selection for index invalidation.

CMCC_MCFGMonitor Configuration Register

Address: 0x4600C028
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
MODE	1:0	Cache Controller Monitor Counter Mode `0` Cycle counter `1` Instruction hit counter, only relevant for unified cache and instruction cache architecture `2` Data hit counter, only relevant for unified cache and data cache architecture

CMCC_MENMonitor Enable Register

Address: 0x4600C02C
Reset: 0x00000000
Access: read/write
Size: 32-bit

1 field

Field	Bits	What it does
MENABLE	0	Cache Controller Monitor Enable

CMCC_MCTRLMonitor Control Register

Address: 0x4600C030
Reset: 0x00000000
Access: write only
Size: 32-bit

1 field

Field	Bits	What it does
SWRST	0	Monitor

CMCC_MSRMonitor Status Register

Address: 0x4600C034
Reset: 0x00000000
Access: read only
Size: 32-bit

1 field

Field	Bits	What it does
EVENT_CNT	31:0	Monitor Event Counter

CMCC_WPMRWrite Protection Mode Register

Address: 0x4600C0E4
Reset: 0x00000000
Access: read/write
Size: 32-bit

3 fields

Field	Bits	What it does
WPCR	2	Write Protection Control Enable
WPCFG	0	Write Protection Configuration Enable
WPKEY	31:8	Write Protection Key `4410691` Writing any other value in this field aborts the write operation of the WPCFG and WPCR bits. Always reads as 0.