The 31 registers of MCSPI (Multi Channel Serial Peripheral Interface), from 0x48018000, with their reset value and every field. The PIC32CX1025MTSH128 has 2920 registers in 63 peripherals, one page each.
MCSPI Multi Channel Serial Peripheral Interface
MCSPI_CRControl Register
Address
0x48018000
Reset
0x00000000
Access
write only
Size
32-bit
9 fields
Field
Bits
What it does
FIFOEN
30
FIFO Enable
LASTXFER
24
Last Transfer
RXFCLR
17
Receive FIFO Clear
TXFCLR
16
Transmit FIFO Clear
REQCLR
12
Request to Clear the Comparison Trigger
SWRST
7
MCSPI Software Reset
SPIDIS
1
MCSPI Disable
SPIEN
0
MCSPI Enable
FIFODIS
31
FIFO Disable
MCSPI_MRMode Register
Address
0x48018004
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
Field
Bits
What it does
PCS
19:16
Peripheral Chip Select
MOSIIE
15
MOSI Inversion Enable
CSIE
14
Chip Select Inversion Enable
TPMEN
13
Two-Pin Mode Enable
CMPMODE
12
Comparison Mode
0 Any character is received and comparison function drives CMP flag.
1 Comparison condition must be met to start reception of all incoming characters until REQCLR is set.
0 External MOSI lines multiplexing is not required via Chip Select lines. When MCSPI_MR.TPMEN=0, MCSPI_TWMR.MIL=1 or MCSPI_TWMR.CSM=0, TMCSMUX must be written to 0.
1 Enables external multiplexing of MOSI lines via Chip Select lines. When MCSPI_MR.TPMEN=1, TMCSMUX must be written to 1 if MCSPI_TWMR.MIL=0 and MCSPI_TWMR.CSM=1.
LSBHALF
8
LSB Timing Selection
LLB
7
Local Loopback Enable
CRCEN
6
CRC Enable
WDRBT
5
Wait for Data Read Before Transfer
MODFDIS
4
Mode Fault Detection
BRSRCCLK
3
Bit Rate Source Clock
0 The peripheral clock is the source clock for the bit rate generation.
1 PMC GCLK is the source clock for the bit rate generation, thus the bit rate can be independent of the core/peripheral clock.
PCSDEC
2
Chip Select Decode
PS
1
Peripheral Select
MSTR
0
Host/Client Mode
DLYBCS
31:24
Delay Between Chip Selects
MCSPI_RDRReceive Data Register
Address
0x48018008
Reset
0x00000000
Access
read only
Size
32-bit
8 fields
Field
Bits
What it does
RD2
23:16
Receive Data
PCS
19:16
Peripheral Chip Select
RD
15:0
Receive Data
RD0
15:0
Receive Data
RD1
15:8
Receive Data
RD0
7:0
Receive Data
RD1
31:16
Receive Data
RD3
31:24
Receive Data
MCSPI_TDRTransmit Data Register
Address
0x4801800C
Reset
0x00000000
Access
write only
Size
32-bit
5 fields
Field
Bits
What it does
LASTXFER
24
Last Transfer
PCS
19:16
Peripheral Chip Select
TD
15:0
Transmit Data
TD0
15:0
Transmit Data
TD1
31:16
Transmit Data
MCSPI_SRStatus Register
Address
0x48018010
Reset
0x00000000
Access
read only
Size
32-bit
23 fields
Field
Bits
What it does
TXFPTEF
30
Transmit FIFO Pointer Error Flag
RXFTHF
29
Receive FIFO Threshold Flag
RXFFF
28
Receive FIFO Full Flag
RXFEF
27
Receive FIFO Empty Flag
TXFTHF
26
Transmit FIFO Threshold Flag (cleared on read)
TXFFF
25
Transmit FIFO Full Flag (cleared on read)
TXFEF
24
Transmit FIFO Empty Flag (cleared on read)
SPIENS
16
MCSPI Enable Status
CRCERR
13
CRC Error (cleared on read)
SFERR
12
Client Frame Error (cleared on read)
CMP
11
Comparison Status (cleared on read)
UNDES
10
Underrun Error Status (Client mode only) (cleared on read)
TXEMPTY
9
Transmission Registers Empty (cleared by writing MCSPI_TDR)
NSSR
8
NSS Rising (cleared on read)
TXBUFE
7
TX Buffer Empty (cleared by writing MCSPI_TCR or MCSPI_TNCR)
RXBUFF
6
RX Buffer Full (cleared by writing MCSPI_RCR or MCSPI_RNCR)
ENDTX
5
End of TX Buffer (cleared by writing MCSPI_TCR or MCSPI_TNCR)
ENDRX
4
End of RX Buffer (cleared by writing MCSPI_RCR or MCSPI_RNCR)
OVRES
3
Overrun Error Status (cleared on read)
MODF
2
Mode Fault Error (cleared on read)
TDRE
1
Transmit Data Register Empty (cleared by writing MCSPI_TDR)
RDRF
0
Receive Data Register Full (cleared by reading MCSPI_RDR)
RXFPTEF
31
Receive FIFO Pointer Error Flag
MCSPI_IERInterrupt Enable Register
Address
0x48018014
Reset
0x00000000
Access
write only
Size
32-bit
21 fields
Field
Bits
What it does
TXFPTEF
30
TXFPTEF Interrupt Enable
RXFTHF
29
RXFTHF Interrupt Enable
RXFFF
28
RXFFF Interrupt Enable
RXFEF
27
RXFEF Interrupt Enable
TXFTHF
26
TXFTHF Interrupt Enable
TXFFF
25
TXFFF Interrupt Enable
TXFEF
24
TXFEF Interrupt Enable
CRCERR
13
CRC Error Interrupt Enable
CMP
11
Comparison Interrupt Enable
UNDES
10
Underrun Error Interrupt Enable
TXEMPTY
9
Transmission Registers Empty Enable
NSSR
8
NSS Rising Interrupt Enable
TXBUFE
7
Transmit Buffer Empty Interrupt Enable
RXBUFF
6
Receive Buffer Full Interrupt Enable
ENDTX
5
End of Transmit Buffer Interrupt Enable
ENDRX
4
End of Receive Buffer Interrupt Enable
OVRES
3
Overrun Error Interrupt Enable
MODF
2
Mode Fault Error Interrupt Enable
TDRE
1
MCSPI Transmit Data Register Empty Interrupt Enable
RDRF
0
Receive Data Register Full Interrupt Enable
RXFPTEF
31
RXFPTEF Interrupt Enable
MCSPI_IDRInterrupt Disable Register
Address
0x48018018
Reset
0x00000000
Access
write only
Size
32-bit
21 fields
Field
Bits
What it does
TXFPTEF
30
TXFPTEF Interrupt Disable
RXFTHF
29
RXFTHF Interrupt Disable
RXFFF
28
RXFFF Interrupt Disable
RXFEF
27
RXFEF Interrupt Disable
TXFTHF
26
TXFTHF Interrupt Disable
TXFFF
25
TXFFF Interrupt Disable
TXFEF
24
TXFEF Interrupt Disable
CRCERR
13
CRC Error Interrupt Disable
CMP
11
Comparison Interrupt Disable
UNDES
10
Underrun Error Interrupt Disable
TXEMPTY
9
Transmission Registers Empty Disable
NSSR
8
NSS Rising Interrupt Disable
TXBUFE
7
Transmit Buffer Empty Interrupt Disable
RXBUFF
6
Receive Buffer Full Interrupt Disable
ENDTX
5
End of Transmit Buffer Interrupt Disable
ENDRX
4
End of Receive Buffer Interrupt Disable
OVRES
3
Overrun Error Interrupt Disable
MODF
2
Mode Fault Error Interrupt Disable
TDRE
1
MCSPI Transmit Data Register Empty Interrupt Disable
RDRF
0
Receive Data Register Full Interrupt Disable
RXFPTEF
31
RXFPTEF Interrupt Disable
MCSPI_IMRInterrupt Mask Register
Address
0x4801801C
Reset
0x00000000
Access
read only
Size
32-bit
21 fields
Field
Bits
What it does
TXFPTEF
30
TXFPTEF Interrupt Mask
RXFTHF
29
RXFTHF Interrupt Mask
RXFFF
28
RXFFF Interrupt Mask
RXFEF
27
RXFEF Interrupt Mask
TXFTHF
26
TXFTHF Interrupt Mask
TXFFF
25
TXFFF Interrupt Mask
TXFEF
24
TXFEF Interrupt Mask
CRCERR
13
CRC Error Interrupt Mask
CMP
11
Comparison Interrupt Mask
UNDES
10
Underrun Error Interrupt Mask
TXEMPTY
9
Transmission Registers Empty Mask
NSSR
8
NSS Rising Interrupt Mask
TXBUFE
7
Transmit Buffer Empty Interrupt Mask
RXBUFF
6
Receive Buffer Full Interrupt Mask
ENDTX
5
End of Transmit Buffer Interrupt Mask
ENDRX
4
End of Receive Buffer Interrupt Mask
OVRES
3
Overrun Error Interrupt Mask
MODF
2
Mode Fault Error Interrupt Mask
TDRE
1
MCSPI Transmit Data Register Empty Interrupt Mask
RDRF
0
Receive Data Register Full Interrupt Mask
RXFPTEF
31
RXFPTEF Interrupt Mask
MCSPI_CSR0Chip Select Register (CS_number = 0)
Address
0x48018030
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
DLYBS
23:16
Delay Before SPCK
SCBR
15:8
Serial Clock Bit Rate
BITS
7:4
Bits Per Transfer
0 8 bits for transfer
1 9 bits for transfer
2 10 bits for transfer
3 11 bits for transfer
4 12 bits for transfer
5 13 bits for transfer
6 14 bits for transfer
7 15 bits for transfer
8 16 bits for transfer
CSAAT
3
Chip Select Active After Transfer
CSNAAT
2
Chip Select Not Active After Transfer (ignored if CSAAT = 1)
NCPHA
1
Clock Phase
CPOL
0
Clock Polarity
DLYBCT
31:24
Delay Between Consecutive Transfers
MCSPI_CSR1Chip Select Register (CS_number = 0)
Address
0x48018034
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
DLYBS
23:16
Delay Before SPCK
SCBR
15:8
Serial Clock Bit Rate
BITS
7:4
Bits Per Transfer
0 8 bits for transfer
1 9 bits for transfer
2 10 bits for transfer
3 11 bits for transfer
4 12 bits for transfer
5 13 bits for transfer
6 14 bits for transfer
7 15 bits for transfer
8 16 bits for transfer
CSAAT
3
Chip Select Active After Transfer
CSNAAT
2
Chip Select Not Active After Transfer (ignored if CSAAT = 1)
NCPHA
1
Clock Phase
CPOL
0
Clock Polarity
DLYBCT
31:24
Delay Between Consecutive Transfers
MCSPI_CSR2Chip Select Register (CS_number = 0)
Address
0x48018038
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
DLYBS
23:16
Delay Before SPCK
SCBR
15:8
Serial Clock Bit Rate
BITS
7:4
Bits Per Transfer
0 8 bits for transfer
1 9 bits for transfer
2 10 bits for transfer
3 11 bits for transfer
4 12 bits for transfer
5 13 bits for transfer
6 14 bits for transfer
7 15 bits for transfer
8 16 bits for transfer
CSAAT
3
Chip Select Active After Transfer
CSNAAT
2
Chip Select Not Active After Transfer (ignored if CSAAT = 1)
NCPHA
1
Clock Phase
CPOL
0
Clock Polarity
DLYBCT
31:24
Delay Between Consecutive Transfers
MCSPI_CSR3Chip Select Register (CS_number = 0)
Address
0x4801803C
Reset
0x00000000
Access
read/write
Size
32-bit
8 fields
Field
Bits
What it does
DLYBS
23:16
Delay Before SPCK
SCBR
15:8
Serial Clock Bit Rate
BITS
7:4
Bits Per Transfer
0 8 bits for transfer
1 9 bits for transfer
2 10 bits for transfer
3 11 bits for transfer
4 12 bits for transfer
5 13 bits for transfer
6 14 bits for transfer
7 15 bits for transfer
8 16 bits for transfer
CSAAT
3
Chip Select Active After Transfer
CSNAAT
2
Chip Select Not Active After Transfer (ignored if CSAAT = 1)
NCPHA
1
Clock Phase
CPOL
0
Clock Polarity
DLYBCT
31:24
Delay Between Consecutive Transfers
MCSPI_FMRFIFO Mode Register
Address
0x48018040
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
RXFTHRES
29:24
Receive FIFO Threshold
TXFTHRES
21:16
Transmit FIFO Threshold
RXRDYM
5:4
Receive Data Register Full Mode
0 RDRF will be at level '1' when at least one unread data is in the Receive FIFO.
1 RDRF will be at level '1' when at least two unread data are in the Receive FIFO. Cannot be used when MCSPI_MR.MSTR =1, or if MCSPI_MR.PS =1.
2 RDRF will be at level '1' when at least four unread data are in the Receive FIFO. Cannot be used when MCSPI_CSRx.BITS is greater than 0, or if MCSPI_MR.MSTR = 1, or if MCSPI_MR.PS = 1.
TXRDYM
1:0
Transmit Data Register Empty Mode
0 TDRE will be at level '1' when at least one data can be written in the Transmit FIFO.
1 TDRE will be at level '1' when at least two data can be written in the Transmit FIFO. Cannot be used if MCSPI_MR.PS =1.
MCSPI_FLRFIFO Level Register
Address
0x48018044
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
RXFL
21:16
Receive FIFO Level
TXFL
5:0
Transmit FIFO Level
MCSPI_CMPRComparison Register
Address
0x48018048
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
Field
Bits
What it does
VAL1
15:0
First Comparison Value for Received Character
VAL2
31:16
Second Comparison Value for Received Character
MCSPI_CRCRCRC Register
Address
0x4801804C
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
Field
Bits
What it does
DHRX
27
Disable Header Receiving
DCRX
26
Disable CRC Receiving
FHE
25
Frame Header Excluded
CRM
24
Continuous Read Mode
FRHL
23:20
Frame Header Length
CRCS
16
CRC Size
0 CRC size is 16 bits.
1 CRC size is 32 bits.
FRL
7:0
Frame Length
MCSPI_TPMRTwo-Pin Mode Register
Address
0x48018050
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
Field
Bits
What it does
OSR
3:2
OverSampling Rate
MIL
1
Multiple Input Lines
CSM
0
Chip Select Mode
MCSPI_TPHRTwo-Pin Header Register
Address
0x48018054
Reset
0x00000000
Access
read only
Size
32-bit
4 fields
Field
Bits
What it does
OSR
6:5
OverSampling Rate
GAIN
4:3
Gain
BOOST
2
Current Boost
CNT
1:0
Frame Counter
MCSPI_WPMRWrite Protection Mode Register
Address
0x480180E4
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
WPCREN
2
Write Protection Control Register Enable
WPITEN
1
Write Protection Interrupt Enable
WPEN
0
Write Protection Enable
WPKEY
31:8
Write Protection Key
5460041 Writing any other value in this field aborts the write operation of WPEN. Always reads as 0.
MCSPI_WPSRWrite Protection Status Register
Address
0x480180E8
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
Field
Bits
What it does
WPVSRC
15:8
Write Protection Violation Source
WPVS
0
Write Protection Violation Status
MCSPI_RPRReceive Pointer Register
Address
0x48018100
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXPTR
31:0
Receive Pointer Register
MCSPI_RCRReceive Counter Register
Address
0x48018104
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXCTR
15:0
Receive Counter Register
MCSPI_TPRTransmit Pointer Register
Address
0x48018108
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXPTR
31:0
Transmit Counter Register
MCSPI_TCRTransmit Counter Register
Address
0x4801810C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXCTR
15:0
Transmit Counter Register
MCSPI_RNPRReceive Next Pointer Register
Address
0x48018110
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXNPTR
31:0
Receive Next Pointer
MCSPI_RNCRReceive Next Counter Register
Address
0x48018114
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
RXNCTR
15:0
Receive Next Counter
MCSPI_TNPRTransmit Next Pointer Register
Address
0x48018118
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXNPTR
31:0
Transmit Next Pointer
MCSPI_TNCRTransmit Next Counter Register
Address
0x4801811C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
Field
Bits
What it does
TXNCTR
15:0
Transmit Counter Next
MCSPI_PTCRTransfer Control Register
Address
0x48018120
Reset
0x00000000
Access
write only
Size
32-bit
9 fields
Field
Bits
What it does
ERRCLR
24
Transfer Bus Error Clear
TXCBDIS
19
Transmitter Circular Buffer Disable
TXCBEN
18
Transmitter Circular Buffer Enable
RXCBDIS
17
Receiver Circular Buffer Disable
RXCBEN
16
Receiver Circular Buffer Enable
TXTDIS
9
Transmitter Transfer Disable
TXTEN
8
Transmitter Transfer Enable
RXTDIS
1
Receiver Transfer Disable
RXTEN
0
Receiver Transfer Enable
MCSPI_PTSRTransfer Status Register
Address
0x48018124
Reset
0x00000000
Access
read only
Size
32-bit
5 fields
Field
Bits
What it does
ERR
24
Transfer Bus Error
TXCBEN
18
Transmitter Circular Buffer Enable
RXCBEN
16
Receiver Circular Buffer Enable
TXTEN
8
Transmitter Transfer Enable
RXTEN
0
Receiver Transfer Enable
MCSPI_PWPMRWrite Protection Mode Register
Address
0x48018128
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
Field
Bits
What it does
WPCREN
2
Write Protection Control Register Enable
WPCTREN
1
Write Protection Counter Registers Enable
WPPTREN
0
Write Protection Pointer Registers Enable
WPKEY
31:8
Write Protection Key
5260355 Writing any other value in this field aborts the write operation. Always reads as 0.
BETA