PIC32CX1025MTSH128 QSPI registers

The 31 registers of QSPI (Quad Serial Peripheral Interface), from 0x40020000, with their reset value and every field. The PIC32CX1025MTSH128 has 2920 registers in 63 peripherals, one page each.

QSPI Quad Serial Peripheral Interface

QSPI_CRControl Register

Address
0x40020000
Reset
0x00000000
Access
write only
Size
32-bit
7 fields
FieldBitsWhat it does
LASTXFER24Last Transfer
RTOUT10Reset Time-out
STTFR9Start Transfer
UPDCFG8Update Configuration
SWRST7QSPI Software Reset
QSPIDIS1QSPI Disable
QSPIEN0QSPI Enable

QSPI_MRMode Register

Address
0x40020004
Reset
0x00000000
Access
read/write
Size
32-bit
7 fields
FieldBitsWhat it does
DLYBCT23:16Delay Between Consecutive Transfers
NBBITS11:8Number Of Bits Per Transfer
  • 0 8 bits for transfer
  • 8 16 bits for transfer
TAMPCLR7Tamper Clear Enable
CSMODE5:4Chip Select Mode
  • 0 The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer.
  • 1 The chip select is deasserted when the bit LASTXFER is written to '1' and the character written in QSPI_TDR.TD has been transferred.
  • 2 The chip select is deasserted systematically after each transfer.
WDRBT2Wait Data Read Before Transfer
  • 0 No effect. In SPI mode, a transfer can be initiated whatever the state of QSPI_RDR is.
  • 1 In SPI mode, a transfer can start only if QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception.
SMM0Serial Memory Mode
  • 0 The QSPI is in SPI mode.
  • 1 The QSPI is in Serial Memory mode.
DLYCS31:24Minimum Inactive QCS Delay

QSPI_RDRReceive Data Register

Address
0x40020008
Reset
0x00000000
Access
read only
Size
32-bit
1 field
FieldBitsWhat it does
RD15:0Receive Data

QSPI_TDRTransmit Data Register

Address
0x4002000C
Reset
0x00000000
Access
write only
Size
32-bit
1 field
FieldBitsWhat it does
TD15:0Transmit Data

QSPI_ISRInterrupt Status Register

Address
0x40020010
Reset
0x00000000
Access
read only
Size
32-bit
16 fields
FieldBitsWhat it does
TOUT17QSPI Time-out
CSRA15Chip Select Rise Autoclear
CSFA14Chip Select Fall Autoclear
QITR13QSPI Interrupt Rise
QITF12QSPI Interrupt Fall
LWRA11Last Write Access (cleared on read)
INSTRE10Instruction End Status (cleared on read)
CSR8Chip Select Rise (cleared on read)
TXBUFE7TX Buffer Empty
RXBUFF6RX Buffer Full
ENDTX5End of TX buffer
ENDRX4End of RX buffer
OVRES3Overrun Error Status (cleared on read)
TXEMPTY2Transmission Registers Empty (cleared by writing QSPI_TDR)
TDRE1Transmit Data Register Empty (cleared by writing QSPI_TDR)
RDRF0Receive Data Register Full (cleared by reading QSPI_RDR)

QSPI_IERInterrupt Enable Register

Address
0x40020014
Reset
0x00000000
Access
write only
Size
32-bit
16 fields
FieldBitsWhat it does
TOUT17QSPI Time-out Interrupt Enable
CSRA15Chip Select Rise Autoclear Interrupt Enable
CSFA14Chip Select Fall Autoclear Interrupt Enable
QITR13QSPI Interrupt Rise Interrupt Enable
QITF12QSPI Interrupt Fall Interrupt Enable
LWRA11Last Write Access Interrupt Enable
INSTRE10Instruction End Interrupt Enable
CSR8Chip Select Rise Interrupt Enable
TXBUFE7Transmit Buffer Empty Interrupt Enable
RXBUFF6Receive Buffer Full Interrupt Enable
ENDTX5End of Transmit Buffer Interrupt Enable
ENDRX4End of Receive Buffer Interrupt Enable
OVRES3Overrun Error Interrupt Enable
TXEMPTY2Transmission Registers Empty Enable
TDRE1Transmit Data Register Empty Interrupt Enable
RDRF0Receive Data Register Full Interrupt Enable

QSPI_IDRInterrupt Disable Register

Address
0x40020018
Reset
0x00000000
Access
write only
Size
32-bit
16 fields
FieldBitsWhat it does
TOUT17QSPI Time-out Interrupt Disable
CSRA15Chip Select Rise Autoclear Interrupt Disable
CSFA14Chip Select Fall Autoclear Interrupt Disable
QITR13QSPI Interrupt Rise Interrupt Disable
QITF12QSPI Interrupt Fall Interrupt Disable
LWRA11Last Write Access Interrupt Disable
INSTRE10Instruction End Interrupt Disable
CSR8Chip Select Rise Interrupt Disable
TXBUFE7Transmit Buffer Empty Interrupt Disable
RXBUFF6Receive Buffer Full Interrupt Disable
ENDTX5End of Transmit Buffer Interrupt Disable
ENDRX4End of Receive Buffer Interrupt Disable
OVRES3Overrun Error Interrupt Disable
TXEMPTY2Transmission Registers Empty Disable
TDRE1Transmit Data Register Empty Interrupt Disable
RDRF0Receive Data Register Full Interrupt Disable

QSPI_IMRInterrupt Mask Register

Address
0x4002001C
Reset
0x00000000
Access
read only
Size
32-bit
16 fields
FieldBitsWhat it does
TOUT17QSPI Time-out Interrupt Mask
CSRA15Chip Select Rise Autoclear Interrupt Mask
CSFA14Chip Select Fall Autoclear Interrupt Mask
QITR13QSPI Interrupt Rise Interrupt Mask
QITF12QSPI Interrupt Fall Interrupt Mask
LWRA11Last Write Access Interrupt Mask
INSTRE10Instruction End Interrupt Mask
CSR8Chip Select Rise Interrupt Mask
TXBUFE7Transmit Buffer Empty Interrupt Mask
RXBUFF6Receive Buffer Full Interrupt Mask
ENDTX5End of Transmit Buffer Interrupt Mask
ENDRX4End of Receive Buffer Interrupt Mask
OVRES3Overrun Error Interrupt Mask
TXEMPTY2Transmission Registers Empty Mask
TDRE1Transmit Data Register Empty Interrupt Mask
RDRF0Receive Data Register Full Interrupt Mask

QSPI_SCRSerial Clock Register

Address
0x40020020
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
DLYBS23:16Delay Before QSCK
CPHA1Clock Phase
CPOL0Clock Polarity

QSPI_SRStatus Register

Address
0x40020024
Reset
0x00000000
Access
read/write
Size
32-bit
5 fields
FieldBitsWhat it does
HIDLE4QSPI Idle
RBUSY3Read Busy
CSS2Chip Select Status
QSPIENS1QSPI Enable Status
SYNCBSY0Synchronization Busy

QSPI_IARInstruction Address Register

Address
0x40020030
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
ADDR31:0Address

QSPI_WICRWrite Instruction Code Register

Address
0x40020034
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
WROPT23:16Write Option Code
WRINST7:0Write Instruction Code

QSPI_IFRInstruction Frame Register

Address
0x40020038
Reset
0x00000000
Access
read/write
Size
32-bit
16 fields
FieldBitsWhat it does
PROTTYP29:28Protocol Type
  • 0 Standard (Q)SPI Protocol
DDRCMDEN26DDR Mode Command Enable
  • 0 Transfer of instruction field is performed in Single Data Rate mode even if DDREN is written to '1'.
  • 1 Transfer of instruction field is performed in Double Data Rate mode if DDREN bit is written to '1'. If DDREN is written to '0', the instruction field is sent in Single Data Rate mode.
DQSEN25DQS Sampling Enable
APBTFRTYP24Peripheral BusTransfer Type
SMRM23Serial Memory Register Mode
NBDUM20:16Number Of Dummy Cycles
DDREN15DDR Mode Enable
  • 0 Transfers are performed in Single Data Rate mode.
  • 1 Transfers are performed in Double Data Rate mode, whereas the instruction field is still transferred in Single Data Rate mode.
CRM14Continuous Read Mode
  • 0 Continuous Read mode is disabled.
  • 1 Continuous Read mode is enabled.
TFRTYP12Data Transfer Type
  • 0 Read/Write of memory register, write of memory page buffer. This configuration implies the following: Either the AHB or the APB interface can be used to initiate the transfer (SMRM bit). Returned data represents the memory register value. If the APB interface is used, the RDRF and TDRE flags help to
  • 1 Read/Write accesses to the memory space. This configuration implies the following: Only the System Bus interface can be used to trigger accesses. Access to random location is possible. Address mask is applied and full size accesses only are performed. Internal optimization algorithm is enabled to mi
ADDRL11:10Address Length
  • 0 8-bit address size
  • 1 16-bit address size
  • 2 24-bit address size
  • 3 32-bit address size
OPTL9:8Option Code Length
  • 0 The option code is 1 bit long.
  • 1 The option code is 2 bits long.
  • 2 The option code is 4 bits long.
  • 3 The option code is 8 bits long.
DATAEN7Data Enable
OPTEN6Option Enable
ADDREN5Address Enable
INSTEN4Instruction Enable
WIDTH3:0Width of Instruction Code, Address, Option Code and Data
  • 0 Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI
  • 1 Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI
  • 2 Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI
  • 3 Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI
  • 4 Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI
  • 5 Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI
  • 6 Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI

QSPI_RICRRead Instruction Code Register

Address
0x4002003C
Reset
0x00000000
Access
read/write
Size
32-bit
2 fields
FieldBitsWhat it does
RDOPT23:16Read Option Code
RDINST7:0Read Instruction Code

QSPI_SMRScrambling Mode Register

Address
0x40020040
Reset
0x00000000
Access
read/write
Size
32-bit
3 fields
FieldBitsWhat it does
SCRKL2Scrambling Key Lock
RVDIS1Scrambling/Unscrambling Random Value Disable
SCREN0Scrambling/Unscrambling Enable
  • 0 The scrambling/unscrambling is disabled.
  • 1 The scrambling/unscrambling is enabled.

QSPI_SKRScrambling Key Register

Address
0x40020044
Reset
0x00000000
Access
write only
Size
32-bit
1 field
FieldBitsWhat it does
USRK31:0User Scrambling Key

QSPI_WRACNTWrite Access Counter Register

Address
0x40020054
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
NBWRA31:0Number of Write Accesses

QSPI_TOUTTimeout Register

Address
0x40020064
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TCNTM15:0Time-out Counter Maximum Value

QSPI_WPMRWrite Protection Mode Register

Address
0x400200E4
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
WPCREN2Write Protection Control Register Enable
WPITEN1Write Protection Interrupt Enable
WPEN0Write Protection Enable
WPKEY31:8Write Protection Key
  • 5329744 Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0.

QSPI_WPSRWrite Protection Status Register

Address
0x400200E8
Reset
0x00000000
Access
read only
Size
32-bit
2 fields
FieldBitsWhat it does
WPVSRC15:8Write Protection Violation Source
WPVS0Write Protection Violation Status

QSPI_RPRReceive Pointer Register

Address
0x40020100
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXPTR31:0Receive Pointer Register

QSPI_RCRReceive Counter Register

Address
0x40020104
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXCTR15:0Receive Counter Register

QSPI_TPRTransmit Pointer Register

Address
0x40020108
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXPTR31:0Transmit Counter Register

QSPI_TCRTransmit Counter Register

Address
0x4002010C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXCTR15:0Transmit Counter Register

QSPI_RNPRReceive Next Pointer Register

Address
0x40020110
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXNPTR31:0Receive Next Pointer

QSPI_RNCRReceive Next Counter Register

Address
0x40020114
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
RXNCTR15:0Receive Next Counter

QSPI_TNPRTransmit Next Pointer Register

Address
0x40020118
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXNPTR31:0Transmit Next Pointer

QSPI_TNCRTransmit Next Counter Register

Address
0x4002011C
Reset
0x00000000
Access
read/write
Size
32-bit
1 field
FieldBitsWhat it does
TXNCTR15:0Transmit Counter Next

QSPI_PTCRTransfer Control Register

Address
0x40020120
Reset
0x00000000
Access
write only
Size
32-bit
9 fields
FieldBitsWhat it does
ERRCLR24Transfer Bus Error Clear
TXCBDIS19Transmitter Circular Buffer Disable
TXCBEN18Transmitter Circular Buffer Enable
RXCBDIS17Receiver Circular Buffer Disable
RXCBEN16Receiver Circular Buffer Enable
TXTDIS9Transmitter Transfer Disable
TXTEN8Transmitter Transfer Enable
RXTDIS1Receiver Transfer Disable
RXTEN0Receiver Transfer Enable

QSPI_PTSRTransfer Status Register

Address
0x40020124
Reset
0x00000000
Access
read only
Size
32-bit
5 fields
FieldBitsWhat it does
ERR24Transfer Bus Error
TXCBEN18Transmitter Circular Buffer Enable
RXCBEN16Receiver Circular Buffer Enable
TXTEN8Transmitter Transfer Enable
RXTEN0Receiver Transfer Enable

QSPI_PWPMRWrite Protection Mode Register

Address
0x40020128
Reset
0x00000000
Access
read/write
Size
32-bit
4 fields
FieldBitsWhat it does
WPCREN2Write Protection Control Register Enable
WPCTREN1Write Protection Counter Registers Enable
WPPTREN0Write Protection Pointer Registers Enable
WPKEY31:8Write Protection Key
  • 5260355 Writing any other value in this field aborts the write operation. Always reads as 0.